On Wed, Jun 23, 2021, Paolo Bonzini wrote: > On 22/06/21 19:57, Sean Christopherson wrote: > > +#if PTTYPE == 32 > > + /* > > + * 32-bit paging requires special handling because bit 7 is ignored if > > + * CR4.PSE=0, not reserved. Clear bit 7 in the gpte if the level is > > + * greater than the last level for which bit 7 is the PAGE_SIZE bit. > > + * > > + * The RHS has bit 7 set iff level < (2 + PSE). If it is clear, bit 7 > > + * is not reserved and does not indicate a large page at this level, > > + * so clear PT_PAGE_SIZE_MASK in gpte if that is the case. > > + */ > > + gpte &= level - (PT32_ROOT_LEVEL + !!mmu->mmu_role.ext.cr4_pse); > > !! is not needed and possibly slightly confusing? (We know it's a single > bit). Ah, I had it backwards. I misremembered the "!!" logic added around the mmu_role helpers, but that was to ensure that e.g. kvm_read_cr4_bits() was squished down into a 0/1 value when setting the mmu_role bit.
