On 07/06/21 09:19, Wanpeng Li wrote:
From: Wanpeng Li <wanpengli@xxxxxxxxxxx>
The value of the current counter register after reset is 0 for both
Intel and AMD, let's do it in kvm, though, the TMCCT is always computed
on-demand and never directly readable.
It's useless though since it's never read except by KVM_SET_LAPIC.
Perhaps instead set TMCCT to 0 in kvm_apic_set_state, instead of keeping
the value that was filled in by KVM_GET_LAPIC?
Paolo
Reviewed-by: Jim Mattson <jmattson@xxxxxxxxxx>
Signed-off-by: Wanpeng Li <wanpengli@xxxxxxxxxxx>
---
v1 -> v2:
* update patch description
arch/x86/kvm/lapic.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
index 6d72d8f..cbfdecd 100644
--- a/arch/x86/kvm/lapic.c
+++ b/arch/x86/kvm/lapic.c
@@ -2352,6 +2352,7 @@ void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event)
kvm_lapic_set_reg(apic, APIC_ICR2, 0);
kvm_lapic_set_reg(apic, APIC_TDCR, 0);
kvm_lapic_set_reg(apic, APIC_TMICT, 0);
+ kvm_lapic_set_reg(apic, APIC_TMCCT, 0);
for (i = 0; i < 8; i++) {
kvm_lapic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
kvm_lapic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
