On Thu, Jun 03, 2021 at 03:13:44PM +1000, David Gibson wrote: > > We can still consider it a single "address space" from the IOMMU > > perspective. What has happened is that the address table is not just a > > 64 bit IOVA, but an extended ~80 bit IOVA formed by "PASID, IOVA". > > True. This does complexify how we represent what IOVA ranges are > valid, though. I'll bet you most implementations don't actually > implement a full 64-bit IOVA, which means we effectively have a large > number of windows from (0..max IOVA) for each valid pasid. This adds > another reason I don't think my concept of IOVA windows is just a > power specific thing. Yes Things rapidly get into weird hardware specific stuff though, the request will be for things like: "ARM PASID&IO page table format from SMMU IP block vXX" Which may have a bunch of (possibly very weird!) format specific data to describe and/or configure it. The uAPI needs to be suitably general here. :( > > If we are already going in the direction of having the IOASID specify > > the page table format and other details, specifying that the page > > tabnle format is the 80 bit "PASID, IOVA" format is a fairly small > > step. > > Well, rather I think userspace needs to request what page table format > it wants and the kernel tells it whether it can oblige or not. Yes, this is what I ment. Jason
