On Tue, May 11, 2021 at 10:42:04AM +0800, Like Xu wrote:
> diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
> index 2f89fd599842..c791765f4761 100644
> --- a/arch/x86/events/intel/core.c
> +++ b/arch/x86/events/intel/core.c
> @@ -3898,31 +3898,49 @@ static struct perf_guest_switch_msr *intel_guest_get_msrs(int *nr, void *data)
> struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
> struct perf_guest_switch_msr *arr = cpuc->guest_switch_msrs;
> u64 intel_ctrl = hybrid(cpuc->pmu, intel_ctrl);
> + u64 pebs_mask = (x86_pmu.flags & PMU_FL_PEBS_ALL) ?
> + cpuc->pebs_enabled : (cpuc->pebs_enabled & PEBS_COUNTER_MASK);
> +
> + *nr = 0;
> + arr[(*nr)++] = (struct perf_guest_switch_msr){
> + .msr = MSR_CORE_PERF_GLOBAL_CTRL,
> + .host = intel_ctrl & ~cpuc->intel_ctrl_guest_mask,
> + .guest = intel_ctrl & (~cpuc->intel_ctrl_host_mask | ~pebs_mask),
> + };
>
> + if (!x86_pmu.pebs)
> + return arr;
>
> + /*
> + * If PMU counter has PEBS enabled it is not enough to
> + * disable counter on a guest entry since PEBS memory
> + * write can overshoot guest entry and corrupt guest
> + * memory. Disabling PEBS solves the problem.
> + *
> + * Don't do this if the CPU already enforces it.
> + */
> + if (x86_pmu.pebs_no_isolation) {
> + arr[(*nr)++] = (struct perf_guest_switch_msr){
> + .msr = MSR_IA32_PEBS_ENABLE,
> + .host = cpuc->pebs_enabled,
> + .guest = 0,
> + };
> + return arr;
> }
>
> + if (!x86_pmu.pebs_vmx)
> + return arr;
> +
> + arr[*nr] = (struct perf_guest_switch_msr){
> + .msr = MSR_IA32_PEBS_ENABLE,
> + .host = cpuc->pebs_enabled & ~cpuc->intel_ctrl_guest_mask,
> + .guest = pebs_mask & ~cpuc->intel_ctrl_host_mask,
> + };
> +
> + /* Set hw GLOBAL_CTRL bits for PEBS counter when it runs for guest */
> + arr[0].guest |= arr[*nr].guest;
> +
> + ++(*nr);
> return arr;
> }
ISTR saying I was confused as heck by this function, I still don't see
clarifying comments :/
What's .host and .guest ?
