Hi Drew, On 4/20/21 7:59 PM, Andrew Jones wrote: > Move secondary_entry helper functions out of .init and into .text, > since secondary_entry isn't run at at "init" time. Actually, anything > that is used after init time should be in .text, as we may not include > .init in some build configurations. > > Reviewed-by Nikos Nikoleris <nikos.nikoleris@xxxxxxx> > Signed-off-by: Andrew Jones <drjones@xxxxxxxxxx> > --- > arm/cstart.S | 66 +++++++++++++++++++++++++++++--------------------- > arm/cstart64.S | 18 ++++++++------ > 2 files changed, 49 insertions(+), 35 deletions(-) > > diff --git a/arm/cstart.S b/arm/cstart.S > index d88a98362940..b2c0ba061cd5 100644 > --- a/arm/cstart.S > +++ b/arm/cstart.S > @@ -96,32 +96,7 @@ start: > bl exit > b halt > > - > -.macro set_mode_stack mode, stack > - add \stack, #S_FRAME_SIZE > - msr cpsr_c, #(\mode | PSR_I_BIT | PSR_F_BIT) > - isb > - mov sp, \stack > -.endm > - > -exceptions_init: > - mrc p15, 0, r2, c1, c0, 0 @ read SCTLR > - bic r2, #CR_V @ SCTLR.V := 0 > - mcr p15, 0, r2, c1, c0, 0 @ write SCTLR > - ldr r2, =vector_table > - mcr p15, 0, r2, c12, c0, 0 @ write VBAR > - > - mrs r2, cpsr > - > - /* first frame reserved for svc mode */ > - set_mode_stack UND_MODE, r0 > - set_mode_stack ABT_MODE, r0 > - set_mode_stack IRQ_MODE, r0 > - set_mode_stack FIQ_MODE, r0 > - > - msr cpsr_cxsf, r2 @ back to svc mode > - isb > - mov pc, lr > +.text > > enable_vfp: > /* Enable full access to CP10 and CP11: */ > @@ -133,8 +108,6 @@ enable_vfp: > vmsr fpexc, r0 > mov pc, lr > > -.text > - > .global get_mmu_off > get_mmu_off: > ldr r0, =auxinfo > @@ -235,6 +208,43 @@ asm_mmu_disable: > > mov pc, lr > > +/* > + * Vectors > + */ > + > +.macro set_mode_stack mode, stack > + add \stack, #S_FRAME_SIZE > + msr cpsr_c, #(\mode | PSR_I_BIT | PSR_F_BIT) > + isb > + mov sp, \stack > +.endm > + > +/* > + * exceptions_init > + * > + * Input r0 is the stack top, which is the exception stacks base > + */ > +exceptions_init: > + mrc p15, 0, r2, c1, c0, 0 @ read SCTLR > + bic r2, #CR_V @ SCTLR.V := 0 > + mcr p15, 0, r2, c1, c0, 0 @ write SCTLR > + ldr r2, =vector_table > + mcr p15, 0, r2, c12, c0, 0 @ write VBAR > + > + mrs r2, cpsr > + > + /* > + * The first frame is reserved for svc mode > + */ > + set_mode_stack UND_MODE, r0 > + set_mode_stack ABT_MODE, r0 > + set_mode_stack IRQ_MODE, r0 > + set_mode_stack FIQ_MODE, r0 > + > + msr cpsr_cxsf, r2 @ back to svc mode > + isb > + mov pc, lr > + > /* > * Vector stubs > * Simplified version of the Linux kernel implementation > diff --git a/arm/cstart64.S b/arm/cstart64.S > index 0a85338bcdae..7963e1fea979 100644 > --- a/arm/cstart64.S > +++ b/arm/cstart64.S > @@ -109,13 +109,6 @@ start: > bl exit > b halt > > -exceptions_init: > - adrp x4, vector_table > - add x4, x4, :lo12:vector_table > - msr vbar_el1, x4 > - isb > - ret > - > .text > > .globl get_mmu_off > @@ -251,6 +244,17 @@ asm_mmu_disable: > > /* > * Vectors > + */ > + > +exceptions_init: > + adrp x4, vector_table > + add x4, x4, :lo12:vector_table > + msr vbar_el1, x4 > + isb > + ret > + > +/* > + * Vector stubs > * Adapted from arch/arm64/kernel/entry.S > */ > .macro vector_stub, name, vec The diff looks nice and clean, exactly what you want from a straightforward move. I checked that the new code matches the old one, but for arm I haven't checked that the code is correct, because I'm not familiar with arm assembly. I also compiled for arm and arm64: Reviewed-by: Alexandru Elisei <alexandru.elisei@xxxxxxx> Thanks, Alex
