On 4/21/21 6:00 AM, Wei Liu wrote:
On Thu, Apr 15, 2021 at 01:43:37PM +0000, Vineeth Pillai wrote:
+/*
+ * This is specific to AMD and specifies that enlightened TLB flush is
+ * supported. If guest opts in to this feature, ASID invalidations only
+ * flushes gva -> hpa mapping entries. To flush the TLB entries derived
+ * from NPT, hypercalls should be used (HvFlushGuestPhysicalAddressSpace
+ * or HvFlushGuestPhysicalAddressList).
+ */
+#define HV_X64_NESTED_ENLIGHTENED_TLB BIT(22)
+
c
This is not yet documented in TLFS, right? I can't find this bit in the
latest edition (6.0b).
This would be documented in the TLFS update which is soon to be
released.
My first thought is the comment says this is AMD specific but the name
is rather generic. That looks a bit odd to begin with.
I thought of of keeping the name generic to avoid renaming Intel
specific ones also. If I understand correctly, the TLFS would also
be having generic name for this and just translated the generic
name here in this header.
Thanks,
Vineeth
