On 29/03/21 10:52, Vitaly Kuznetsov wrote:
Paolo Bonzini <pbonzini@xxxxxxxxxx> writes:
On 23/03/21 09:45, Vitaly Kuznetsov wrote:
MSR_F15H_PERF_CTL0-5, MSR_F15H_PERF_CTR0-5 MSRs are only available when
X86_FEATURE_PERFCTR_CORE CPUID bit was exposed to the guest. KVM, however,
allows these MSRs unconditionally because kvm_pmu_is_valid_msr() ->
amd_msr_idx_to_pmc() check always passes and because kvm_pmu_set_msr() ->
amd_pmu_set_msr() doesn't fail.
In case of a counter (CTRn), no big harm is done as we only increase
internal PMC's value but in case of an eventsel (CTLn), we go deep into
perf internals with a non-existing counter.
Note, kvm_get_msr_common() just returns '0' when these MSRs don't exist
and this also seems to contradict architectural behavior which is #GP
(I did check one old Opteron host) but changing this status quo is a bit
scarier.
Hmm, since these do have a cpuid bit it may not be that scary.
Well, if you're not scared I can send a patch)
Go ahead.
Paolo
