On Tue, Mar 23, 2021 at 11:16 AM Jim Mattson <jmattson@xxxxxxxxxx> wrote: > > On Mon, Mar 22, 2021 at 7:37 PM <lihaiwei.kernel@xxxxxxxxx> wrote: > > > > From: Haiwei Li <lihaiwei@xxxxxxxxxxx> > > > > According to IA-32 SDM Vol.3D "A.1 BASIC VMX INFORMATION", two inspections > > are missing. > > * Bit 31 is always 0. Earlier versions of this manual specified that the > > VMCS revision identifier was a 32-bit field in bits 31:0 of this MSR. For > > all processors produced prior to this change, bit 31 of this MSR was read > > as 0. > > For all *Intel* processors produced prior to this change, bit 31 of > this MSR may have been 0. However, a conforming hypervisor may have > selected a full 32-bit VMCS revision identifier with the high bit set > for nested VMX. Furthermore, there are other vendors, such as VIA, > which have implemented the VMX extensions, and they, too, may have > selected a full 32-bit VMCS revision identifier with the high bit set. > Intel should know better than to change the documentation after the > horse is out of the barn. Got it, thanks. > > What, exactly, is the value you are adding with this check? I did this just to match the sdm. -- Haiwei Li
