On Wed, 3 Mar 2021 16:45:05 +0000, Marc Zyngier wrote:
> It recently became apparent that the ARMv8 architecture has interesting
> rules regarding attributes being used when fetching instructions
> if the MMU is off at Stage-1.
>
> In this situation, the CPU is allowed to fetch from the PoC and
> allocate into the I-cache (unless the memory is mapped with
> the XN attribute at Stage-2).
>
> [...]
Applied to fixes, thanks!
[1/1] KVM: arm64: Ensure I-cache isolation between vcpus of a same VM
commit: 01dc9262ff5797b675c32c0c6bc682777d23de05
Cheers,
M.
--
Without deviation from the norm, progress is not possible.
