On Sat, Mar 06, 2021 at 10:54:47AM +0000, Marc Zyngier wrote: > On Fri, 05 Mar 2021 19:07:09 +0000, > Catalin Marinas <catalin.marinas@xxxxxxx> wrote: > > > > On Wed, Mar 03, 2021 at 04:45:05PM +0000, Marc Zyngier wrote: > > > It recently became apparent that the ARMv8 architecture has interesting > > > rules regarding attributes being used when fetching instructions > > > if the MMU is off at Stage-1. > > > > > > In this situation, the CPU is allowed to fetch from the PoC and > > > allocate into the I-cache (unless the memory is mapped with > > > the XN attribute at Stage-2). > > > > Digging through the ARM ARM is hard. Do we have this behaviour with FWB > > as well? > > The ARM ARM doesn't seem to mention FWB at all when it comes to > instruction fetch, which is sort of expected as it only covers the > D-side. I *think* we could sidestep this when CTR_EL0.DIC is set > though, as the I-side would then snoop the D-side. Not sure this helps. CTR_EL0.DIC refers to the need for maintenance to PoU while the SCTLR_EL1.M == 0 causes the I-cache to fetch from PoC. I don't think I-cache snooping the D-cache would happen to the PoU when the S1 MMU is off. My reading of D4.4.4 is that when SCTLR_EL1.M == 0 both I and D accesses are Normal Non-cacheable with a note in D4.4.6 that Non-cacheable accesses may be held in the I-cache. The FWB rules on combining S1 and S2 says that Normal Non-cacheable at S1 is "upgraded" to cacheable. This should happen irrespective of whether the S1 MMU is on or off and should apply to both I and D accesses (since it does not explicitly says). So I think we could skip this IC IALLU when FWB is present. The same logic should apply when the VMM copies the VM text. With FWB, we probably only need D-cache maintenance to PoU and only if CTR_EL0.IDC==0. I haven't checked what the code currently does. -- Catalin
