The dcache_by_line_op macro executes a DSB to complete the cache maintenance operations. According to ARM DDI 0487G.a, page B2-150: "In addition, no instruction that appears in program order after the DSB instruction can alter any state of the system or perform any part of its functionality until the DSB completes other than: - Being fetched from memory and decoded. - Reading the general-purpose, SIMD and floating-point, Special-purpose, or System registers that are directly or indirectly read without causing side-effects." Similar definition for ARM in ARM DDI 0406C.d, page A3-150: "In addition, no instruction that appears in program order after the DSB instruction can execute until the DSB completes." This means that we don't need the ISB to prevent reordering of the cache maintenance instructions. We are also not doing icache maintenance, where an ISB would be required for the PE to discard instructions speculated before the invalidation. In conclusion, the ISB is unnecessary, so remove it. Signed-off-by: Alexandru Elisei <alexandru.elisei@xxxxxxx> --- arm/cstart.S | 1 - arm/cstart64.S | 1 - 2 files changed, 2 deletions(-) diff --git a/arm/cstart.S b/arm/cstart.S index 954748b00f64..2d62c1e6d40d 100644 --- a/arm/cstart.S +++ b/arm/cstart.S @@ -212,7 +212,6 @@ asm_mmu_disable: ldr r1, [r1] sub r1, r1, r0 dcache_by_line_op dccimvac, sy, r0, r1, r2, r3 - isb mov pc, lr diff --git a/arm/cstart64.S b/arm/cstart64.S index 046bd3914098..c1deff842f03 100644 --- a/arm/cstart64.S +++ b/arm/cstart64.S @@ -219,7 +219,6 @@ asm_mmu_disable: ldr x1, [x1, :lo12:__phys_end] sub x1, x1, x0 dcache_by_line_op civac, sy, x0, x1, x2, x3 - isb ret -- 2.30.1
