On 11/11/20 03:42, Xu, Like wrote:
Hi Peter,
On 2020/11/11 4:52, Stephane Eranian wrote:
On Tue, Nov 10, 2020 at 7:37 AM Peter Zijlstra<peterz@xxxxxxxxxxxxx>
wrote:
On Tue, Nov 10, 2020 at 04:12:57PM +0100, Peter Zijlstra wrote:
On Mon, Nov 09, 2020 at 10:12:37AM +0800, Like Xu wrote:
The Precise Event Based Sampling(PEBS) supported on Intel Ice Lake
server
platforms can provide an architectural state of the instruction
executed
after the instruction that caused the event. This patch set enables
the
the PEBS via DS feature for KVM (also non) Linux guest on the Ice
Lake.
The Linux guest can use PEBS feature like native:
# perf record -e instructions:ppp ./br_instr a
# perf record -c 100000 -e instructions:pp ./br_instr a
If the counter_freezing is not enabled on the host, the guest PEBS
will
be disabled on purpose when host is using PEBS facility. By default,
KVM disables the co-existence of guest PEBS and host PEBS.
Thanks Stephane for clarifying the use cases for Freeze-on-[PMI|Overflow].
Please let me express it more clearly.
The goal of the whole patch set is to enable guest PEBS, regardless of
whether the counter_freezing is frozen or not. By default, it will not
support both the guest and the host to use PEBS at the same time.
Please continue reviewing the patch set, especially for the slow path
we proposed this time and related host perf changes:
- add intel_pmu_handle_guest_pebs() to __intel_pmu_pebs_event();
- add switch MSRs (PEBS_ENABLE, DS_AREA, DATA_CFG) to
intel_guest_get_msrs();
- the construction of incoming parameters for
perf_event_create_kernel_counter();
I believe if you understand the general idea, the comments will be very
valuable.
What is the state of this work? I was expecting a new version that
doesn't use counter_freezing. However, I see that counter_freezing is
still in there, so this patch from Peter has never been applied.
Paolo
