Hi Marc, On 1/15/21 5:42 PM, Marc Zyngier wrote: > Hi Eric, > > On 2021-01-15 14:01, Auger Eric wrote: >> Hi Marc, >> >> On 1/14/21 11:56 AM, Marc Zyngier wrote: >>> Upgrading the PMU code from ARMv8.1 to ARMv8.4 turns out to be >>> pretty easy. All that is required is support for PMMIR_EL1, which >>> is read-only, and for which returning 0 is a valid option. >>> >>> Let's just do that and adjust what we return to the guest. >>> >>> Signed-off-by: Marc Zyngier <maz@xxxxxxxxxx> >>> --- >>> arch/arm64/kvm/sys_regs.c | 5 +++-- >>> 1 file changed, 3 insertions(+), 2 deletions(-) >>> >>> diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c >>> index 8f79ec1fffa7..2f4ecbd2abfb 100644 >>> --- a/arch/arm64/kvm/sys_regs.c >>> +++ b/arch/arm64/kvm/sys_regs.c >>> @@ -1051,10 +1051,10 @@ static u64 read_id_reg(const struct kvm_vcpu >>> *vcpu, >>> /* Limit debug to ARMv8.0 */ >>> val &= ~FEATURE(ID_AA64DFR0_DEBUGVER); >>> val |= FIELD_PREP(FEATURE(ID_AA64DFR0_DEBUGVER), 6); >>> - /* Limit guests to PMUv3 for ARMv8.1 */ >>> + /* Limit guests to PMUv3 for ARMv8.4 */ >>> val = cpuid_feature_cap_perfmon_field(val, >>> ID_AA64DFR0_PMUVER_SHIFT, >>> - kvm_vcpu_has_pmu(vcpu) ? >>> ID_AA64DFR0_PMUVER_8_1 : 0); >>> + kvm_vcpu_has_pmu(vcpu) ? >>> ID_AA64DFR0_PMUVER_8_4 : 0); >>> break; >>> case SYS_ID_DFR0_EL1: >>> /* Limit guests to PMUv3 for ARMv8.1 */ >> what about the debug version in aarch32 state. Is it on purpose that you >> leave it as 8_1? > > That's a good point. There is also the fact that we keep reporting > STALL_SLOT as a valid event even in PMCEID0_EL1 despite PMMIR_EL1.SLOTS > always reporting 0. Hum OK. I did not notice that ;-) Thanks Eric > > I'll fix that and resend something next week. > > Thanks, > > M.
