On 12/15/20 11:57 PM, Philippe Mathieu-Daudé wrote: > Philippe Mathieu-Daudé (24): > target/mips/translate: Extract decode_opc_legacy() from decode_opc() > target/mips/translate: Expose check_mips_64() to 32-bit mode > target/mips/cpu: Introduce isa_rel6_available() helper > target/mips: Introduce ase_msa_available() helper > target/mips: Simplify msa_reset() > target/mips: Use CP0_Config3 to set MIPS_HFLAG_MSA > target/mips: Simplify MSA TCG logic > target/mips: Remove now unused ASE_MSA definition > target/mips: Alias MSA vector registers on FPU scalar registers > target/mips: Extract msa_translate_init() from mips_tcg_init() > target/mips: Remove CPUMIPSState* argument from gen_msa*() methods > target/mips: Explode gen_msa_branch() as gen_msa_BxZ_V/BxZ() > target/mips: Rename msa_helper.c as mod-msa_helper.c > target/mips: Move msa_reset() to mod-msa_helper.c > target/mips: Extract MSA helpers from op_helper.c > target/mips: Extract MSA helper definitions > target/mips: Declare gen_msa/_branch() in 'translate.h' > target/mips: Extract MSA translation routines > target/mips: Introduce decode tree bindings for MSA opcodes > target/mips: Use decode_ase_msa() generated from decodetree > target/mips: Extract LSA/DLSA translation generators > target/mips: Introduce decodetree helpers for MSA LSA/DLSA opcodes > target/mips: Introduce decodetree helpers for Release6 LSA/DLSA > opcodes > target/mips/mod-msa: Pass TCGCond argument to gen_check_zero_element() Thanks, series queued to mips-next (without patch #3 "Introduce isa_rel6_available helper").
