在 2020/12/16 上午7:48, Philippe Mathieu-Daudé 写道:
On 12/16/20 12:27 AM, Richard Henderson wrote:
On 12/15/20 4:57 PM, Philippe Mathieu-Daudé wrote:
+bool isa_rel6_available(const CPUMIPSState *env)
+{
+ if (TARGET_LONG_BITS == 64) {
+ return cpu_supports_isa(env, ISA_MIPS64R6);
+ }
+ return cpu_supports_isa(env, ISA_MIPS32R6);
+}
So... does qemu-system-mips64 support 32-bit cpus?
Well... TBH I never tested it :S It looks the TCG code
is compiled with 64-bit TL registers, the machine address
space is 64-bit regardless the CPU, and I see various
#ifdef MIPS64 code that look dubious with 32-bit CPU.
qemu-system-mips64 and qemu-system-mips64el do support 32bit
CPUs like M14Kc and P5600 :-)
Sometimes I'm just curious about the necessity of having mips/mipsel
targets
If so, this needs to be written
if (TARGET_LONG_BITS == 64 && cpu_supports_isa(...)) {
return true;
}
Otherwise, this will return false for a mips32r6 cpu.
I see. Rel6 is new to me, so I'll have to look at the ISA
manuals before returning to this thread with an answer.
TBH I do think it doesn't sounds like a good idea to make 32-bit
and 64-bit different. In fact ISA_MIPS32R6 is always set for targets
with ISA_MIPS64R6.
We're treating MIPS64R6 as a superset of MIPS32R6, and ISA_MIPS3
is used to tell if a CPU supports 64-bit.
FYI: https://commons.wikimedia.org/wiki/File:MIPS_instruction_set_family.svg
Thanks.
- Jiaxun
Thanks for reviewing the series!
Phil.
