Hi Eric, > -----Original Message----- > From: kvmarm-bounces@xxxxxxxxxxxxxxxxxxxxx > [mailto:kvmarm-bounces@xxxxxxxxxxxxxxxxxxxxx] On Behalf Of Auger Eric > Sent: 01 December 2020 13:59 > To: wangxingang <wangxingang5@xxxxxxxxxx> > Cc: Xieyingtai <xieyingtai@xxxxxxxxxx>; jean-philippe@xxxxxxxxxx; > kvm@xxxxxxxxxxxxxxx; maz@xxxxxxxxxx; joro@xxxxxxxxxx; will@xxxxxxxxxx; > iommu@xxxxxxxxxxxxxxxxxxxxxxxxxx; linux-kernel@xxxxxxxxxxxxxxx; > vivek.gautam@xxxxxxx; alex.williamson@xxxxxxxxxx; > zhangfei.gao@xxxxxxxxxx; robin.murphy@xxxxxxx; > kvmarm@xxxxxxxxxxxxxxxxxxxxx; eric.auger.pro@xxxxxxxxx > Subject: Re: [PATCH v13 07/15] iommu/smmuv3: Allow stage 1 invalidation with > unmanaged ASIDs > > Hi Xingang, > > On 12/1/20 2:33 PM, Xingang Wang wrote: > > Hi Eric > > > > On Wed, 18 Nov 2020 12:21:43, Eric Auger wrote: > >> @@ -1710,7 +1710,11 @@ static void arm_smmu_tlb_inv_context(void > *cookie) > >> * insertion to guarantee those are observed before the TLBI. Do be > >> * careful, 007. > >> */ > >> - if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1) { > >> + if (ext_asid >= 0) { /* guest stage 1 invalidation */ > >> + cmd.opcode = CMDQ_OP_TLBI_NH_ASID; > >> + cmd.tlbi.asid = ext_asid; > >> + cmd.tlbi.vmid = smmu_domain->s2_cfg.vmid; > >> + } else if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1) { > > > > Found a problem here, the cmd for guest stage 1 invalidation is built, > > but it is not delivered to smmu. > > > > Thank you for the report. I will fix that soon. With that fixed, have > you been able to run vSVA on top of the series. Do you need other stuff > to be fixed at SMMU level? I am seeing another issue with this series. This is when you have the vSMMU in non-strict mode(iommu.strict=0). Any network pass-through dev with iperf run will be enough to reproduce the issue. It may randomly stop/hang. It looks like the .flush_iotlb_all from guest is not propagated down to the host correctly. I have a temp hack to fix this in Qemu wherein CMDQ_OP_TLBI_NH_ASID will result in a CACHE_INVALIDATE with IOMMU_INV_GRANU_PASID flag and archid set. Please take a look and let me know. As I am going to respin soon, please let me > know what is the best branch to rebase to alleviate your integration. Please find the latest kernel and Qemu branch with vSVA support added here, https://github.com/hisilicon/kernel-dev/tree/5.10-rc4-2stage-v13-vsva https://github.com/hisilicon/qemu/tree/v5.2.0-rc1-2stage-rfcv7-vsva I have done some basic minimum vSVA tests on a HiSilicon D06 board with a zip dev that supports STALL. All looks good so far apart from the issues that have been already reported/discussed. The kernel branch is actually a rebase of sva/uacce related patches from a Linaro branch here, https://github.com/Linaro/linux-kernel-uadk/tree/uacce-devel-5.10 I think going forward it will be good(if possible) to respin your series on top of a sva branch with STALL/PRI support added. Hi Jean/zhangfei, Is it possible to have a branch with minimum required SVA/UACCE related patches that are already public and can be a "stable" candidate for future respin of Eric's series? Please share your thoughts. Thanks, Shameer > Best Regards > > Eric > > _______________________________________________ > kvmarm mailing list > kvmarm@xxxxxxxxxxxxxxxxxxxxx > https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
