On Thu, Nov 26, 2020 at 02:34:05PM +0000, Marc Zyngier wrote: > On 2020-11-26 14:32, Andrew Jones wrote: > > On Thu, Nov 26, 2020 at 02:13:44PM +0000, Marc Zyngier wrote: > > > On 2020-11-26 13:46, Andrew Jones wrote: > > > > Not counting TnD, which KVM doesn't currently consider, CSSELR_EL1 > > > > can have a maximum value of 0b1101 (13), which corresponds to an > > > > instruction cache at level 7. With CSSELR_MAX set to 12 we can > > > > only select up to cache level 6. Change it to 14. > > > > > > > > Signed-off-by: Andrew Jones <drjones@xxxxxxxxxx> > > > > --- > > > > arch/arm64/kvm/sys_regs.c | 2 +- > > > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > > > > > diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c > > > > index c1fac9836af1..ef453f7827fa 100644 > > > > --- a/arch/arm64/kvm/sys_regs.c > > > > +++ b/arch/arm64/kvm/sys_regs.c > > > > @@ -169,7 +169,7 @@ void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 > > > > val, int reg) > > > > static u32 cache_levels; > > > > > > > > /* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */ > > > > -#define CSSELR_MAX 12 > > > > +#define CSSELR_MAX 14 > > > > > > > > /* Which cache CCSIDR represents depends on CSSELR value. */ > > > > static u32 get_ccsidr(u32 csselr) > > > > > > Huh, nice catch. Do we need a CC: stable tag for this? > > > > > > > Hi Marc, > > > > I wasn't thinking so, because I'm not expecting there to actually > > be hardware with seven cache levels in the wild any time soon. You > > have more knowledge about what's out there and coming, though, so > > feel free CC stable if needed. > > That's actually what I was wondering, whether you had seen that in the > wild already. Since you haven't (and I'm not aware of such a monstrosity), > I'll queue it for 5.11. > > Do you want me to take the selftest stuff at the same time? > Yes, please :) Thanks, drew
