On Mon, Oct 26, 2020 at 01:34:46PM +0000, Marc Zyngier wrote:
> Move the AArch64 exception injection code from EL1 to HYP, leaving
> only the ESR_EL1 updates to EL1. In order to come with the differences
> between VHE and nVHE, two set of system register accessors are provided.
>
> SPSR, ELR, PC and PSTATE are now completely handled in the hypervisor.
>
> Signed-off-by: Marc Zyngier <maz@xxxxxxxxxx>
> void kvm_inject_exception(struct kvm_vcpu *vcpu)
> {
> + switch (vcpu->arch.flags & KVM_ARM64_EXCEPT_MASK) {
> + case KVM_ARM64_EXCEPT_AA64_EL1_SYNC:
> + enter_exception64(vcpu, PSR_MODE_EL1h, except_type_sync);
> + break;
> + case KVM_ARM64_EXCEPT_AA64_EL1_IRQ:
> + enter_exception64(vcpu, PSR_MODE_EL1h, except_type_irq);
> + break;
> + case KVM_ARM64_EXCEPT_AA64_EL1_FIQ:
> + enter_exception64(vcpu, PSR_MODE_EL1h, except_type_fiq);
> + break;
> + case KVM_ARM64_EXCEPT_AA64_EL1_SERR:
> + enter_exception64(vcpu, PSR_MODE_EL1h, except_type_serror);
> + break;
> + default:
> + /* EL2 are unimplemented until we get NV. One day. */
> + break;
> + }
> }
Huh, we're going to allow EL1 to inject IRQ/FIQ/SERROR *exceptions*
directly, rather than pending those via HCR_EL2.{VI,VF,VSE}? We never
used to have code to do that.
If we're going to support that we'll need to check against the DAIF bits
to make sure we don't inject an exception that can't be architecturally
taken.
I guess we'll tighten that up along with the synchronous exception
checks, but given those three cases aren't needed today it might be
worth removing them from the switch for now and/or adding a comment to
that effect.
Thanks,
Mark.
