On Fri, Sep 11, 2020 at 09:28:34AM +0200, Paolo Bonzini wrote:
> On 10/09/20 09:01, Philippe Mathieu-Daudé wrote:
> > In order to use inclusive terminology, rename 'slave stream'
> > as 'sink stream'.
> >
> > Signed-off-by: Philippe Mathieu-Daudé <philmd@xxxxxxxxxx>
> > ---
> > hw/dma/xilinx_axidma.c | 26 +++++++++++++-------------
> > 1 file changed, 13 insertions(+), 13 deletions(-)
> >
> > diff --git a/hw/dma/xilinx_axidma.c b/hw/dma/xilinx_axidma.c
> > index cf12a852ea1..19e14a2997e 100644
> > --- a/hw/dma/xilinx_axidma.c
> > +++ b/hw/dma/xilinx_axidma.c
> > @@ -46,11 +46,11 @@
> > OBJECT_CHECK(XilinxAXIDMA, (obj), TYPE_XILINX_AXI_DMA)
> >
> > #define XILINX_AXI_DMA_DATA_STREAM(obj) \
> > - OBJECT_CHECK(XilinxAXIDMAStreamSlave, (obj),\
> > + OBJECT_CHECK(XilinxAXIDMAStreamSink, (obj),\
> > TYPE_XILINX_AXI_DMA_DATA_STREAM)
> >
> > #define XILINX_AXI_DMA_CONTROL_STREAM(obj) \
> > - OBJECT_CHECK(XilinxAXIDMAStreamSlave, (obj),\
> > + OBJECT_CHECK(XilinxAXIDMAStreamSink, (obj),\
> > TYPE_XILINX_AXI_DMA_CONTROL_STREAM)
> >
> > #define R_DMACR (0x00 / 4)
> > @@ -63,7 +63,7 @@
> > #define CONTROL_PAYLOAD_SIZE (CONTROL_PAYLOAD_WORDS * (sizeof(uint32_t)))
> >
> > typedef struct XilinxAXIDMA XilinxAXIDMA;
> > -typedef struct XilinxAXIDMAStreamSlave XilinxAXIDMAStreamSlave;
> > +typedef struct XilinxAXIDMAStreamSink XilinxAXIDMAStreamSink;
> >
> > enum {
> > DMACR_RUNSTOP = 1,
> > @@ -118,7 +118,7 @@ struct Stream {
> > unsigned char txbuf[16 * 1024];
> > };
> >
> > -struct XilinxAXIDMAStreamSlave {
> > +struct XilinxAXIDMAStreamSink {
> > Object parent;
> >
> > struct XilinxAXIDMA *dma;
> > @@ -133,8 +133,8 @@ struct XilinxAXIDMA {
> > uint32_t freqhz;
> > StreamSink *tx_data_dev;
> > StreamSink *tx_control_dev;
> > - XilinxAXIDMAStreamSlave rx_data_dev;
> > - XilinxAXIDMAStreamSlave rx_control_dev;
> > + XilinxAXIDMAStreamSink rx_data_dev;
> > + XilinxAXIDMAStreamSink rx_control_dev;
> >
> > struct Stream streams[2];
> >
> > @@ -390,7 +390,7 @@ static size_t
> > xilinx_axidma_control_stream_push(StreamSink *obj, unsigned char *buf,
> > size_t len, bool eop)
> > {
> > - XilinxAXIDMAStreamSlave *cs = XILINX_AXI_DMA_CONTROL_STREAM(obj);
> > + XilinxAXIDMAStreamSink *cs = XILINX_AXI_DMA_CONTROL_STREAM(obj);
> > struct Stream *s = &cs->dma->streams[1];
> >
> > if (len != CONTROL_PAYLOAD_SIZE) {
> > @@ -407,7 +407,7 @@ xilinx_axidma_data_stream_can_push(StreamSink *obj,
> > StreamCanPushNotifyFn notify,
> > void *notify_opaque)
> > {
> > - XilinxAXIDMAStreamSlave *ds = XILINX_AXI_DMA_DATA_STREAM(obj);
> > + XilinxAXIDMAStreamSink *ds = XILINX_AXI_DMA_DATA_STREAM(obj);
> > struct Stream *s = &ds->dma->streams[1];
> >
> > if (!stream_running(s) || stream_idle(s)) {
> > @@ -423,7 +423,7 @@ static size_t
> > xilinx_axidma_data_stream_push(StreamSink *obj, unsigned char *buf, size_t len,
> > bool eop)
> > {
> > - XilinxAXIDMAStreamSlave *ds = XILINX_AXI_DMA_DATA_STREAM(obj);
> > + XilinxAXIDMAStreamSink *ds = XILINX_AXI_DMA_DATA_STREAM(obj);
> > struct Stream *s = &ds->dma->streams[1];
> > size_t ret;
> >
> > @@ -534,8 +534,8 @@ static const MemoryRegionOps axidma_ops = {
> > static void xilinx_axidma_realize(DeviceState *dev, Error **errp)
> > {
> > XilinxAXIDMA *s = XILINX_AXI_DMA(dev);
> > - XilinxAXIDMAStreamSlave *ds = XILINX_AXI_DMA_DATA_STREAM(&s->rx_data_dev);
> > - XilinxAXIDMAStreamSlave *cs = XILINX_AXI_DMA_CONTROL_STREAM(
> > + XilinxAXIDMAStreamSink *ds = XILINX_AXI_DMA_DATA_STREAM(&s->rx_data_dev);
> > + XilinxAXIDMAStreamSink *cs = XILINX_AXI_DMA_CONTROL_STREAM(
> > &s->rx_control_dev);
> > int i;
> >
> > @@ -634,7 +634,7 @@ static const TypeInfo axidma_info = {
> > static const TypeInfo xilinx_axidma_data_stream_info = {
> > .name = TYPE_XILINX_AXI_DMA_DATA_STREAM,
> > .parent = TYPE_OBJECT,
> > - .instance_size = sizeof(struct XilinxAXIDMAStreamSlave),
> > + .instance_size = sizeof(struct XilinxAXIDMAStreamSink),
> > .class_init = xilinx_axidma_stream_class_init,
> > .class_data = &xilinx_axidma_data_stream_class,
> > .interfaces = (InterfaceInfo[]) {
> > @@ -646,7 +646,7 @@ static const TypeInfo xilinx_axidma_data_stream_info = {
> > static const TypeInfo xilinx_axidma_control_stream_info = {
> > .name = TYPE_XILINX_AXI_DMA_CONTROL_STREAM,
> > .parent = TYPE_OBJECT,
> > - .instance_size = sizeof(struct XilinxAXIDMAStreamSlave),
> > + .instance_size = sizeof(struct XilinxAXIDMAStreamSink),
> > .class_init = xilinx_axidma_stream_class_init,
> > .class_data = &xilinx_axidma_control_stream_class,
> > .interfaces = (InterfaceInfo[]) {
> >
>
> Acked-by: Paolo Bonzini <pbonzini@xxxxxxxxxx>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xxxxxxxxxx>
