On Wed, Aug 12, 2020 at 02:30:37PM +0800, Wanpeng Li wrote: > From: Wanpeng Li <wanpengli@xxxxxxxxxxx> > > Return 0 when getting the tscdeadline timer if the lapic is hw disabled. It'd be helpful to reference the SDM for the general behavior of the MSR. In other timer modes (LVT bit 18 = 0), the IA32_TSC_DEADLINE MSR reads zero and writes are ignored. I'd also vote to squash the two patches together, they really are paired changes to match the architectural behavior. Reviewed-by: Sean Christopherson <sean.j.christopherson@xxxxxxxxx>
