On Thu, Aug 6, 2020 at 5:47 PM Babu Moger <babu.moger@xxxxxxx> wrote: > > The following intercept bit has been added to support VMEXIT > for INVPCID instruction: > Code Name Cause > A2h VMEXIT_INVPCID INVPCID instruction > > The following bit has been added to the VMCB layout control area > to control intercept of INVPCID: > Byte Offset Bit(s) Function > 14h 2 intercept INVPCID > > Enable the interceptions when the the guest is running with shadow > page table enabled and handle the tlbflush based on the invpcid > instruction type. > > For the guests with nested page table (NPT) support, the INVPCID > feature works as running it natively. KVM does not need to do any > special handling in this case. > > AMD documentation for INVPCID feature is available at "AMD64 > Architecture Programmer’s Manual Volume 2: System Programming, > Pub. 24593 Rev. 3.34(or later)" > > The documentation can be obtained at the links below: > Link: https://www.amd.com/system/files/TechDocs/24593.pdf > Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537 > > Signed-off-by: Babu Moger <babu.moger@xxxxxxx> Reviewed-by: Jim Mattson <jmattson@xxxxxxxxxx>
