On Tue, 21 Jul 2020 at 23:25, Sean Christopherson
<sean.j.christopherson@xxxxxxxxx> wrote:
>
> On Tue, Jul 21, 2020 at 12:35:01PM +0200, Vitaly Kuznetsov wrote:
> > Wanpeng Li <kernellwp@xxxxxxxxx> writes:
> >
> > > From: Wanpeng Li <wanpengli@xxxxxxxxxxx>
> > >
> > > Prevent setting the tscdeadline timer if the lapic is hw disabled.
> > >
> > > Signed-off-by: Wanpeng Li <wanpengli@xxxxxxxxxxx>
>
> A Fixes and/or Cc stable is probably needed for this.
>
> > > ---
> > > arch/x86/kvm/lapic.c | 2 +-
> > > 1 file changed, 1 insertion(+), 1 deletion(-)
> > >
> > > diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
> > > index 5bf72fc..4ce2ddd 100644
> > > --- a/arch/x86/kvm/lapic.c
> > > +++ b/arch/x86/kvm/lapic.c
> > > @@ -2195,7 +2195,7 @@ void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data)
> > > {
> > > struct kvm_lapic *apic = vcpu->arch.apic;
> > >
> > > - if (!lapic_in_kernel(vcpu) || apic_lvtt_oneshot(apic) ||
> > > + if (!kvm_apic_present(vcpu) || apic_lvtt_oneshot(apic) ||
> > > apic_lvtt_period(apic))
> > > return;
> >
> > Out of pure curiosity, what is the architectural behavior if I disable
> > LAPIC, write to IA32_TSC_DEADLINE and then re-enable LAPIC before the
> > timer was supposed to fire?
>
> Intel's SDM reserves the right for the CPU to do whatever it wants :-)
>
> When IA32_APIC_BASE[11] is set to 0, prior initialization to the APIC
> may be lost and the APIC may return to the state described in Section
> 10.4.7.1, “Local APIC State After Power-Up or Reset.”
>
> Practically speaking, resetting APIC state seems like the sane approach,
> i.e. KVM should probably call kvm_lapic_reset() when the APIC transitions
> from HW enabled -> disabled. Maybe in a follow-up patch to this one?
kvm_lapic_reset() will call the set base logic, a little recursive in
the codes, it can be done after this recursion is solved.
Wanpeng
