On Thu, 23 Jul 2020 16:12:20 +0530
Ravi Bangoria <ravi.bangoria@xxxxxxxxxxxxx> wrote:
> As per the PAPR, bit 0 of byte 64 in pa-features property indicates
> availability of 2nd DAWR registers. i.e. If this bit is set, 2nd
> DAWR is present, otherwise not. Use KVM_CAP_PPC_DAWR1 capability to
> find whether kvm supports 2nd DAWR or nor. If it's supported, set
> the pa-feature bit in guest DT so the guest kernel can support 2nd
> DAWR.
>
> Signed-off-by: Ravi Bangoria <ravi.bangoria@xxxxxxxxxxxxx>
> ---
> hw/ppc/spapr.c | 33 +++++++++++++++++++++++++++++++++
> include/hw/ppc/spapr.h | 1 +
> linux-headers/asm-powerpc/kvm.h | 4 ++++
> linux-headers/linux/kvm.h | 1 +
> target/ppc/cpu.h | 2 ++
> target/ppc/kvm.c | 7 +++++++
> target/ppc/kvm_ppc.h | 6 ++++++
> target/ppc/translate_init.inc.c | 17 ++++++++++++++++-
> 8 files changed, 70 insertions(+), 1 deletion(-)
>
(...)
> diff --git a/linux-headers/asm-powerpc/kvm.h b/linux-headers/asm-powerpc/kvm.h
> index 38d61b73f5..c5c0f128b4 100644
> --- a/linux-headers/asm-powerpc/kvm.h
> +++ b/linux-headers/asm-powerpc/kvm.h
> @@ -640,6 +640,10 @@ struct kvm_ppc_cpu_char {
> #define KVM_REG_PPC_ONLINE (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xbf)
> #define KVM_REG_PPC_PTCR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc0)
>
> +/* POWER10 registers. */
> +#define KVM_REG_PPC_DAWR1 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc1)
> +#define KVM_REG_PPC_DAWRX1 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc2)
> +
> /* Transactional Memory checkpointed state:
> * This is all GPRs, all VSX regs and a subset of SPRs
> */
> diff --git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h
> index a28c366737..015fa4b44b 100644
> --- a/linux-headers/linux/kvm.h
> +++ b/linux-headers/linux/kvm.h
> @@ -1031,6 +1031,7 @@ struct kvm_ppc_resize_hpt {
> #define KVM_CAP_PPC_SECURE_GUEST 181
> #define KVM_CAP_HALT_POLL 182
> #define KVM_CAP_ASYNC_PF_INT 183
> +#define KVM_CAP_PPC_DAWR1 184
>
> #ifdef KVM_CAP_IRQ_ROUTING
Same here, this should go together with the headers changes from the
first patch.
