Athira Rajeev <atrajeev@xxxxxxxxxxxxxxxxxx> writes: >> On 22-Jul-2020, at 10:11 AM, Jordan Niethe <jniethe5@xxxxxxxxx> wrote: >> >> On Sat, Jul 18, 2020 at 1:13 AM Athira Rajeev >> <atrajeev@xxxxxxxxxxxxxxxxxx <mailto:atrajeev@xxxxxxxxxxxxxxxxxx>> wrote: >>> >>> From: Madhavan Srinivasan <maddy@xxxxxxxxxxxxx> >>> >>> Add power10 feature function to dt_cpu_ftrs.c along >>> with a power10 specific init() to initialize pmu sprs, >>> sets the oprofile_cpu_type and cpu_features. This will >>> enable performance monitoring unit(PMU) for Power10 >>> in CPU features with "performance-monitor-power10". >>> >>> For PowerISA v3.1, BHRB disable is controlled via Monitor Mode >>> Control Register A (MMCRA) bit, namely "BHRB Recording Disable >>> (BHRBRD)". This patch initializes MMCRA BHRBRD to disable BHRB >>> feature at boot for power10. >>> >>> Signed-off-by: Madhavan Srinivasan <maddy@xxxxxxxxxxxxx> >>> --- >>> arch/powerpc/include/asm/reg.h | 3 +++ >>> arch/powerpc/kernel/cpu_setup_power.S | 8 ++++++++ >>> arch/powerpc/kernel/dt_cpu_ftrs.c | 26 ++++++++++++++++++++++++++ >>> 3 files changed, 37 insertions(+) >>> >>> diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h >>> index 21a1b2d..900ada1 100644 >>> --- a/arch/powerpc/include/asm/reg.h >>> +++ b/arch/powerpc/include/asm/reg.h >>> @@ -1068,6 +1068,9 @@ >>> #define MMCR0_PMC2_LOADMISSTIME 0x5 >>> #endif >>> >>> +/* BHRB disable bit for PowerISA v3.10 */ >>> +#define MMCRA_BHRB_DISABLE 0x0000002000000000 >> Shouldn't this go under SPRN_MMCRA with the other MMCRA_*. > > > Hi Jordan > > Ok, the definition of MMCRA is under #ifdef for 64 bit . if I move definition of MMCRA_BHRB_DISABLE along with other SPR's, I also > need to define this for 32-bit to satisfy core-book3s to compile as below: > > diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h > index 900ada10762c..7e271657b412 100644 > --- a/arch/powerpc/include/asm/reg.h > +++ b/arch/powerpc/include/asm/reg.h > @@ -888,6 +888,8 @@ > #define MMCRA_SLOT 0x07000000UL /* SLOT bits (37-39) */ > #define MMCRA_SLOT_SHIFT 24 > #define MMCRA_SAMPLE_ENABLE 0x00000001UL /* enable sampling */ > +/* BHRB disable bit for PowerISA v3.10 */ > +#define MMCRA_BHRB_DISABLE 0x0000002000000000 I changed it to: #define MMCRA_BHRB_DISABLE 0x2000000000UL // BHRB disable bit for ISA v3.1 >>> diff --git a/arch/powerpc/kernel/cpu_setup_power.S b/arch/powerpc/kernel/cpu_setup_power.S >>> index efdcfa7..b8e0d1e 100644 >>> --- a/arch/powerpc/kernel/cpu_setup_power.S >>> +++ b/arch/powerpc/kernel/cpu_setup_power.S >>> @@ -94,6 +94,7 @@ _GLOBAL(__restore_cpu_power8) >>> _GLOBAL(__setup_cpu_power10) >>> mflr r11 >>> bl __init_FSCR_power10 >>> + bl __init_PMU_ISA31 >> So we set MMCRA here but then aren't we still going to call __init_PMU >> which will overwrite that? >> Would this setting MMCRA also need to be handled in __restore_cpu_power10? > > Thanks for this nice catch ! When I rebased code initial phase, we didn’t had power10 part filled in. > It was a miss from my side in adding PMu init functions and thanks for pointing this out. > Below patch will call __init_PMU functions in setup and restore. Please check if this looks good Actually those changes should be in a separate patch. This one is wiring up DT CPU features, the cpu setup routines are not used by DT CPU features. So please send a new patch I can insert into the series that adds the cpu_setup_power.S changes. cheers > -- > diff --git a/arch/powerpc/kernel/cpu_setup_power.S b/arch/powerpc/kernel/cpu_setup_power.S > index efdcfa714106..e672a6c5fd7c 100644 > --- a/arch/powerpc/kernel/cpu_setup_power.S > +++ b/arch/powerpc/kernel/cpu_setup_power.S > @@ -94,6 +94,9 @@ _GLOBAL(__restore_cpu_power8) > _GLOBAL(__setup_cpu_power10) > mflr r11 > bl __init_FSCR_power10 > + bl __init_PMU > + bl __init_PMU_ISA31 > + bl __init_PMU_HV > b 1f > > _GLOBAL(__setup_cpu_power9) > @@ -124,6 +127,9 @@ _GLOBAL(__setup_cpu_power9) > _GLOBAL(__restore_cpu_power10) > mflr r11 > bl __init_FSCR_power10 > + bl __init_PMU > + bl __init_PMU_ISA31 > + bl __init_PMU_HV > b 1f > > _GLOBAL(__restore_cpu_power9) > @@ -233,3 +239,10 @@ __init_PMU_ISA207: > li r5,0 > mtspr SPRN_MMCRS,r5 > blr > + > +__init_PMU_ISA31: > + li r5,0 > + mtspr SPRN_MMCR3,r5 > + LOAD_REG_IMMEDIATE(r5, MMCRA_BHRB_DISABLE) > + mtspr SPRN_MMCRA,r5 > + blr >
