On 09/07/20 01:07, Jim Mattson wrote: >> Just curious about using LME instead of LMA. According to APM, >> >> " The processor behaves as a 32-bit x86 processor in all respects >> until long mode is activated, even if long mode is enabled. None of the >> new 64-bit data sizes, addressing, or system aspects available in long >> mode can be used until EFER.LMA=1." >> >> >> Is it possible that L1 sets LME, but not LMA, in L2's VMCS and this >> code will execute even if the processor is not in long-mode ? > > No. EFER.LMA is not modifiable through software. It is always > "EFER.LME != 0 && CR0.PG != 0." In fact, AMD doesn't specify (unlike Intel) that EFER.LME, CR0.PG and EFER.LMA must be consistent, and for SMM state restore they say that "The EFER.LMA register bit is set to the value obtained by logically ANDing the SMRAM values of EFER.LME, CR0.PG, and CR4.PAE". So it is plausible that they ignore completely EFER.LMA in the VMCB. I quickly tried hacking svm_set_efer to set or reset it, and it works either way. EFLAGS.VM from the VMCB is also ignored if the processor is in long mode just like the APM says in "10.4 Leaving SMM"! Paolo
