> From: Stefan Hajnoczi <stefanha@xxxxxxxxx> > Sent: Monday, June 29, 2020 5:22 PM > > On Wed, Jun 24, 2020 at 01:55:26AM -0700, Liu Yi L wrote: > > +Details can be found in Documentation/userspace-api/iommu.rst. For > > +Intel VT-d, each stage 1 page table is bound to host by: > > + > > + nesting_op->flags = VFIO_IOMMU_NESTING_OP_BIND_PGTBL; > > + memcpy(&nesting_op->data, &bind_data, sizeof(bind_data)); > > + ioctl(container->fd, VFIO_IOMMU_NESTING_OP, nesting_op); > > + > > +As mentioned above, guest OS may use stage 1 for GIOVA->GPA or GVA->GPA. > > +GVA->GPA page tables are available when PASID (Process Address Space > > +GVA->ID) > > +is exposed to guest. e.g. guest with PASID-capable devices assigned. > > +For such page table binding, the bind_data should include PASID info, > > +which is allocated by guest itself or by host. This depends on > > +hardware vendor e.g. Intel VT-d requires to allocate PASID from host. > > +This requirement is defined by the Virtual Command Support in VT-d > > +3.0 spec, guest software running on VT-d should allocate PASID from > > +host kernel. To allocate PASID from host, user space should +check > > +the IOMMU_NESTING_FEAT_SYSWIDE_PASID > > s/+check/check/g got it. > Reviewed-by: Stefan Hajnoczi <stefanha@xxxxxxxxxx> thanks :-) Regards, Yi Liu
