On 22/06/20 19:57, Tom Lendacky wrote: >>> In bare-metal, there's no guarantee a CPU will report all the faults in a >>> single PF error code. And because of race conditions, software can never >>> rely on that behavior. Whenever the OS thinks it has cured an error, it >>> must always be able to handle another #PF for the same access when it >>> retries because another processor could have modified the PTE in the >>> meantime. >> I agree, but I don't understand the relation to this patch. Can you >> explain? > > I guess I'm trying to understand why RSVD has to be reported to the guest > on a #PF (vs an NPF) when there's no guarantee that it can receive that > error code today even when guest MAXPHYADDR == host MAXPHYADDR. That would > eliminate the need to trap #PF. That's an interesting observation! But do processors exist where either: 1) RSVD doesn't win over all other bits, assuming no race conditions 2) A/D bits can be clobbered in a page table entry that has reserved bits set? Running the x86/access.flat testcase from kvm-unit-tests on bare metal suggests that all existing processors do neither of the above. In particular, the second would be a showstopper on AMD. Paolo
