On 22/06/20 17:08, Mohammed Gamal wrote: >> Also, something to consider. On AMD, when memory encryption is >> enabled (via the SYS_CFG MSR), a guest can actually have a larger >> MAXPHYADDR than the host. How do these patches all play into that? As long as the NPT page tables handle the guest MAXPHYADDR just fine, there's no need to do anything. I think that's the case? Paolo > Well the patches definitely don't address that case. It's assumed a > guest VM's MAXPHYADDR <= host MAXPHYADDR, and hence we handle the case > where a guests's physical address space is smaller and try to trap > faults that may go unnoticed by the host. > > My question is in the case of guest MAXPHYADDR > host MAXPHYADDR, do we > expect somehow that there might be guest physical addresses that > contain what the host could see as reserved bits? And how'd the host > handle that?
