This MSR is only available when the host supports WAITPKG feature. This breaks a L2 guest, if the L0 is set to ignore the unknown MSRs, because the only other safety check that the L1 kernel does is an attempt to read the MSR, and it succeeds since L0 ignores that read. This makes L1 kernel to inform its qemu that MSR_IA32_UMWAIT_CONTROL is a supported MSR but later on when qemu attempts to set it in the host state this fails since it is not supported. Fixes: 6e3ba4abcea56 (KVM: vmx: Emulate MSR IA32_UMWAIT_CONTROL) Signed-off-by: Maxim Levitsky <mlevitsk@xxxxxxxxxx> Reviewed-by: Sean Christopherson <sean.j.christopherson@xxxxxxxxx> Reviewed-by: Krish Sadhukhan <krish.sadhukhan@xxxxxxxxxx> --- arch/x86/kvm/x86.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index b226fb8abe41b..4752293312947 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -5316,6 +5316,10 @@ static void kvm_init_msr_list(void) min(INTEL_PMC_MAX_GENERIC, x86_pmu.num_counters_gp)) continue; break; + case MSR_IA32_UMWAIT_CONTROL: + if (!kvm_cpu_cap_has(X86_FEATURE_WAITPKG)) + continue; + break; default: break; } -- 2.26.2
