On 2020-05-25 20:57, Thomas Huth wrote:
On 18/05/2020 18.07, Pierre Morel wrote:
While adding the definition for the AFP-Register control bit, move all
existing definitions for CR0 out of the C zone to the assmbler zone to
keep the definitions concerning CR0 together.
Signed-off-by: Pierre Morel <pmorel@xxxxxxxxxxxxx>
Reviewed-by: David Hildenbrand <david@xxxxxxxxxx>
Reviewed-by: Janosch Frank <frankja@xxxxxxxxxxxxx>
Reviewed-by: Cornelia Huck <cohuck@xxxxxxxxxx>
---
lib/s390x/asm/arch_def.h | 11 ++++++-----
s390x/cstart64.S | 2 +-
2 files changed, 7 insertions(+), 6 deletions(-)
diff --git a/lib/s390x/asm/arch_def.h b/lib/s390x/asm/arch_def.h
index 820af93..54ffd0b 100644
--- a/lib/s390x/asm/arch_def.h
+++ b/lib/s390x/asm/arch_def.h
@@ -19,17 +19,18 @@
#define PSW_EXCEPTION_MASK (PSW_MASK_EA | PSW_MASK_BA)
+#define CR0_EXTM_SCLP 0X0000000000000200UL
+#define CR0_EXTM_EXTC 0X0000000000002000UL
+#define CR0_EXTM_EMGC 0X0000000000004000UL
+#define CR0_EXTM_MASK 0X0000000000006200UL
+#define CR0_AFP_REG_CRTL 0x0000000000040000UL
+
#ifndef __ASSEMBLER__
struct psw {
uint64_t mask;
uint64_t addr;
};
-#define CR0_EXTM_SCLP 0X0000000000000200UL
-#define CR0_EXTM_EXTC 0X0000000000002000UL
-#define CR0_EXTM_EMGC 0X0000000000004000UL
-#define CR0_EXTM_MASK 0X0000000000006200UL
This patch does not apply anymore due to commit f7df29115f736b ...
please switch to lower-case "0x"s in the next version.
Thanks,
Thomas
OK, I will rebase.
Thanks,
Pierre
--
Pierre Morel
IBM Lab Boeblingen
