On Thu, Apr 30, 2020 at 10:31:32AM +0200, Vitaly Kuznetsov wrote: > as we need to write to two MSRs to configure the new mechanism ordering > becomes important. If the guest writes to ASYNC_PF_EN first to establish > the shared memory stucture the interrupt in ASYNC_PF2 is not yet set > (and AFAIR '0' is a valid interrupt!) so if an async pf happens > immediately after that we'll be forced to inject INT0 in the guest and > it'll get confused and linkely miss the event. > > We can probably mandate the reverse sequence: guest has to set up > interrupt in ASYNC_PF2 first and then write to ASYNC_PF_EN (with both > bit 0 and bit 3). In that case the additional 'enable' bit in ASYNC_PF2 > seems redundant. This protocol doesn't look too complex for guests to > follow. Yep looks good. We should also update the document too about the fact. Thanks, -- Peter Xu
