On Thu, Apr 23, 2020 at 10:20:32AM -0700, Sean Christopherson wrote:
> On Thu, Mar 26, 2020 at 04:18:41PM +0800, Yang Weijiang wrote:
> > CR4.CET is master control bit for CET function.
> > There're mutual constrains between CR0.WP and CR4.CET, so need
> > to check the dependent bit while changing the control registers.
> >
> > Note:
> > 1)The processor does not allow CR4.CET to be set if CR0.WP = 0,
> > similarly, it does not allow CR0.WP to be cleared while
> > CR4.CET = 1. In either case, KVM would inject #GP to guest.
>
> Nit: the CET vs. WP dependency and #GP belongs in the "main" part of the
> changelog, as it's the crux of the patch. Item (2) below is more along
> the lines of "note" material.
>
OK, will change it, thank you!
> >
> > 2)SHSTK and IBT features share one control MSR:
> > MSR_IA32_{U,S}_CET, which means it's difficult to hide
> > one feature from another in the case of SHSTK != IBT,
> > after discussed in community, it's agreed to allow guest
> > control two features independently as it won't introduce
> > security hole.
> >
>
