While adding the definition for the AFP-Register control bit, move all
existing definitions for CR0 out of the C zone to the assmbler zone to
keep the definitions concerning CR0 together.
Signed-off-by: Pierre Morel <pmorel@xxxxxxxxxxxxx>
Reviewed-by: David Hildenbrand <david@xxxxxxxxxx>
Reviewed-by: Janosch Frank <frankja@xxxxxxxxxxxxx>
Reviewed-by: Cornelia Huck <cohuck@xxxxxxxxxx>
---
lib/s390x/asm/arch_def.h | 11 ++++++-----
s390x/cstart64.S | 2 +-
2 files changed, 7 insertions(+), 6 deletions(-)
diff --git a/lib/s390x/asm/arch_def.h b/lib/s390x/asm/arch_def.h
index c54409a..a0d2362 100644
--- a/lib/s390x/asm/arch_def.h
+++ b/lib/s390x/asm/arch_def.h
@@ -20,17 +20,18 @@
#define PSW_EXCEPTION_MASK (PSW_MASK_EA | PSW_MASK_BA)
#define PSW_RESET_MASK (PSW_EXCEPTION_MASK | PSW_MASK_SHORT_PSW)
+#define CR0_EXTM_SCLP 0X0000000000000200UL
+#define CR0_EXTM_EXTC 0X0000000000002000UL
+#define CR0_EXTM_EMGC 0X0000000000004000UL
+#define CR0_EXTM_MASK 0X0000000000006200UL
+#define CR0_AFP_REG_CRTL 0x0000000000040000UL
+
#ifndef __ASSEMBLER__
struct psw {
uint64_t mask;
uint64_t addr;
};
-#define CR0_EXTM_SCLP 0X0000000000000200UL
-#define CR0_EXTM_EXTC 0X0000000000002000UL
-#define CR0_EXTM_EMGC 0X0000000000004000UL
-#define CR0_EXTM_MASK 0X0000000000006200UL
-
struct lowcore {
uint8_t pad_0x0000[0x0080 - 0x0000]; /* 0x0000 */
uint32_t ext_int_param; /* 0x0080 */
diff --git a/s390x/cstart64.S b/s390x/cstart64.S
index e394b3a..2906e39 100644
--- a/s390x/cstart64.S
+++ b/s390x/cstart64.S
@@ -241,4 +241,4 @@ svc_int_psw:
.quad PSW_EXCEPTION_MASK, svc_int
initial_cr0:
/* enable AFP-register control, so FP regs (+BFP instr) can be used */
- .quad 0x0000000000040000
+ .quad CR0_AFP_REG_CRTL
--
2.25.1
