IPI and Timer cause the main vmexits in cloud environment observation, after single target IPI fastpath, let's optimize tscdeadline timer latency by introducing tscdeadline timer emulation fastpath, it will skip various KVM related checks when possible. i.e. after vmexit due to tscdeadline timer emulation, handle it and vmentry immediately without checking various kvm stuff when possible. Testing on SKX Server. cyclictest in guest(w/o mwait exposed, adaptive advance lapic timer is default -1): 5632.75ns -> 4559.25ns, 19% kvm-unit-test/vmexit.flat: w/o APICv, w/o advance timer: tscdeadline_immed: 4780.75 -> 3851 19.4% tscdeadline: 7474 -> 6528.5 12.7% w/o APICv, w/ adaptive advance timer default -1: tscdeadline_immed: 4845.75 -> 3930.5 18.9% tscdeadline: 6048 -> 5871.75 3% w/ APICv, w/o avanced timer: tscdeadline_immed: 2919 -> 2467.75 15.5% tscdeadline: 5661.75 -> 5188.25 8.4% w/ APICv, w/ adaptive advance timer default -1: tscdeadline_immed: 3018.5 -> 2561 15.2% tscdeadline: 4663.75 -> 4537 2.7% Tested-by: Haiwei Li <lihaiwei@xxxxxxxxxxx> Cc: Haiwei Li <lihaiwei@xxxxxxxxxxx> v1 -> v2: * move more stuff from vmx.c to lapic.c * remove redundant checking * check more conditions to bail out CONT_RUN * not break AMD * not handle LVTT sepecial * cleanup codes Wanpeng Li (5): KVM: LAPIC: Introduce interrupt delivery fastpath KVM: X86: Introduce need_cancel_enter_guest helper KVM: VMX: Introduce generic fastpath handler KVM: X86: TSCDEADLINE MSR emulation fastpath KVM: VMX: Handle preemption timer fastpath arch/x86/include/asm/kvm_host.h | 2 + arch/x86/kvm/lapic.c | 98 +++++++++++++++++++++++++++++++++++++++-- arch/x86/kvm/lapic.h | 2 + arch/x86/kvm/svm/avic.c | 5 +++ arch/x86/kvm/svm/svm.c | 1 + arch/x86/kvm/svm/svm.h | 1 + arch/x86/kvm/vmx/vmx.c | 69 ++++++++++++++++++++++++----- arch/x86/kvm/x86.c | 42 ++++++++++++++---- arch/x86/kvm/x86.h | 1 + 9 files changed, 199 insertions(+), 22 deletions(-) -- 2.7.4
