Paolo Bonzini <pbonzini@xxxxxxxxxx> writes:
> The test_ioapic_physical_destination_mode uses destination id 1, so it
> cannot be run with only one processor. Fixing that however shows that
> the self-reconfiguration test is broken with split irqchip. This should
> be fixed in QEMU.
>
> Signed-off-by: Paolo Bonzini <pbonzini@xxxxxxxxxx>
> ---
> x86/ioapic.c | 3 ++-
> x86/unittests.cfg | 3 ++-
> 2 files changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/x86/ioapic.c b/x86/ioapic.c
> index 3106531..ad0b47d 100644
> --- a/x86/ioapic.c
> +++ b/x86/ioapic.c
> @@ -504,11 +504,12 @@ int main(void)
> test_ioapic_level_tmr(true);
> test_ioapic_edge_tmr(true);
>
> - test_ioapic_physical_destination_mode();
> if (cpu_count() > 3)
> test_ioapic_logical_destination_mode();
>
> if (cpu_count() > 1) {
> + test_ioapic_physical_destination_mode();
> +
> test_ioapic_edge_tmr_smp(false);
> test_ioapic_level_tmr_smp(false);
> test_ioapic_level_tmr_smp(true);
> diff --git a/x86/unittests.cfg b/x86/unittests.cfg
> index d658bc8..a4df06b 100644
> --- a/x86/unittests.cfg
> +++ b/x86/unittests.cfg
> @@ -33,7 +33,8 @@ arch = x86_64
>
> [ioapic-split]
> file = ioapic.flat
> -extra_params = -cpu qemu64 -machine kernel_irqchip=split
> +smp = 4
> +extra_params = -cpu qemu64,+x2apic -machine kernel_irqchip=split
> arch = x86_64
Thank you but this particular change causes the test to start failing for me:
timeout -k 1s --foreground 90s /usr/libexec/qemu-kvm --no-reboot -nodefaults -device pc-testdev -device isa-debug-exit,iobase=0xf4,iosize=0x4 -vnc none -serial stdio -device pci-testdev -machine accel=kvm -kernel x86/ioapic.flat -smp 4 -cpu qemu64,+x2apic -machine kernel_irqchip=split # -initrd /tmp/tmp.OcMOvh1e7x
enabling apic
enabling apic
enabling apic
enabling apic
paging enabled
cr0 = 80010011
cr3 = 61d000
cr4 = 20
x2apic enabled
PASS: version register read only test
PASS: id register only bits [24:27] writable
PASS: arbitration register set by id
PASS: arbtration register read only
PASS: edge triggered intr
PASS: level triggered intr
PASS: ioapic simultaneous edge interrupts
PASS: coalesce simultaneous level interrupts
PASS: sequential level interrupts
PASS: retriggered level interrupts without masking
PASS: masked level interrupt
PASS: unmasked level interrupt
PASS: masked level interrupt
PASS: unmasked level interrupt
PASS: retriggered level interrupts with mask
PASS: TMR for ioapic edge interrupts (expected false)
PASS: TMR for ioapic level interrupts (expected false)
PASS: TMR for ioapic level interrupts (expected true)
PASS: TMR for ioapic edge interrupts (expected true)
PASS: ioapic logical destination mode
PASS: ioapic physical destination mode
1001569 iterations before interrupt received
PASS: TMR for ioapic edge interrupts (expected false)
1010633 iterations before interrupt received
PASS: TMR for ioapic level interrupts (expected false)
1022574 iterations before interrupt received
PASS: TMR for ioapic level interrupts (expected true)
1010590 iterations before interrupt received
PASS: TMR for ioapic edge interrupts (expected true)
FAIL: Reconfigure self
SUMMARY: 26 tests, 1 unexpected failures
>
> [apic]
--
Vitaly
