its_enable_defaults() enable LPIs at redistributor level
and ITS level.
gicv3_enable_defaults must be called before.
Signed-off-by: Eric Auger <eric.auger@xxxxxxxxxx>
Reviewed-by: Zenghui Yu <yuzenghui@xxxxxxxxxx>
---
v6 -> v7:
- use for_each_present_cpu in its_enable_defaults
v5 -> v6:
- gicv3_lpi_set/get_config introduced before this patch
- dist/redist in commit msg
- Added Zenghui's R-b
v4 -> v5:
- some reformattings moved to earlier patch
- add assert(!gicv3_redist_base()) in alloc_lpi_tables()
- revert the usage of for_each_present_cpu()
v3 -> v4:
- use GITS_BASER_INDIRECT & GITS_BASER_VALID in its_setup_baser()
- don't parse BASERs again in its_enable_defaults
- rename its_setup_baser into its_baser_alloc_table
- All allocations moved to the init function
- squashed "arm/arm64: gicv3: Enable/Disable LPIs at re-distributor level"
into this patch
- introduce gicv3_lpi_rdist_enable and gicv3_lpi_rdist_disable
- pend and prop table bases stored as virt addresses
- move some init functions from enable() to its_init
- removed GICR_PROPBASER_IDBITS_MASK
- introduced LPI_OFFSET
- lpi_prop becomes u8 *
- gicv3_lpi_set_config/get_config became macro
- renamed gicv3_lpi_set_pending_table_bit into gicv3_lpi_set_clr_pending
v2 -> v3:
- introduce its_setup_baser in this patch
- squash "arm/arm64: ITS: Init the command queue" in this patch.
---
lib/arm/asm/gic-v3.h | 6 ++++++
lib/arm/gic-v3.c | 25 +++++++++++++++++++++++++
lib/arm64/asm/gic-v3-its.h | 1 +
lib/arm64/gic-v3-its.c | 13 +++++++++++++
4 files changed, 45 insertions(+)
diff --git a/lib/arm/asm/gic-v3.h b/lib/arm/asm/gic-v3.h
index fedffa8..cb72922 100644
--- a/lib/arm/asm/gic-v3.h
+++ b/lib/arm/asm/gic-v3.h
@@ -57,6 +57,10 @@
#define LPI_PROP_DEFAULT_PRIO 0xa0
#define LPI_PROP_DEFAULT (LPI_PROP_DEFAULT_PRIO | LPI_PROP_GROUP1 | LPI_PROP_ENABLED)
+#define LPI_ID_BASE 8192
+#define LPI(lpi) ((lpi) + LPI_ID_BASE)
+#define LPI_OFFSET(intid) ((intid) - LPI_ID_BASE)
+
#include <asm/arch_gicv3.h>
#ifndef __ASSEMBLY__
@@ -93,6 +97,8 @@ extern void gicv3_ipi_send_mask(int irq, const cpumask_t *dest);
extern void gicv3_set_redist_base(size_t stride);
extern void gicv3_lpi_set_clr_pending(int rdist, int n, bool set);
extern void gicv3_lpi_alloc_tables(void);
+extern void gicv3_lpi_rdist_enable(int redist);
+extern void gicv3_lpi_rdist_disable(int redist);
static inline void gicv3_do_wait_for_rwp(void *base)
{
diff --git a/lib/arm/gic-v3.c b/lib/arm/gic-v3.c
index 6cf1d1d..a7e2cb8 100644
--- a/lib/arm/gic-v3.c
+++ b/lib/arm/gic-v3.c
@@ -199,4 +199,29 @@ void gicv3_lpi_set_clr_pending(int rdist, int n, bool set)
byte &= ~mask;
*ptr = byte;
}
+
+static void gicv3_lpi_rdist_ctrl(u32 redist, bool set)
+{
+ void *ptr;
+ u64 val;
+
+ assert(redist < nr_cpus);
+
+ ptr = gicv3_data.redist_base[redist];
+ val = readl(ptr + GICR_CTLR);
+ if (set)
+ val |= GICR_CTLR_ENABLE_LPIS;
+ else
+ val &= ~GICR_CTLR_ENABLE_LPIS;
+ writel(val, ptr + GICR_CTLR);
+}
+
+void gicv3_lpi_rdist_enable(int redist)
+{
+ gicv3_lpi_rdist_ctrl(redist, true);
+}
+void gicv3_lpi_rdist_disable(int redist)
+{
+ gicv3_lpi_rdist_ctrl(redist, false);
+}
#endif /* __aarch64__ */
diff --git a/lib/arm64/asm/gic-v3-its.h b/lib/arm64/asm/gic-v3-its.h
index 30f2d90..4683011 100644
--- a/lib/arm64/asm/gic-v3-its.h
+++ b/lib/arm64/asm/gic-v3-its.h
@@ -92,5 +92,6 @@ extern struct its_data its_data;
extern void its_parse_typer(void);
extern void its_init(void);
extern int its_baser_lookup(int i, struct its_baser *baser);
+extern void its_enable_defaults(void);
#endif /* _ASMARM64_GIC_V3_ITS_H_ */
diff --git a/lib/arm64/gic-v3-its.c b/lib/arm64/gic-v3-its.c
index fb8e3f2..afc66a3 100644
--- a/lib/arm64/gic-v3-its.c
+++ b/lib/arm64/gic-v3-its.c
@@ -96,3 +96,16 @@ void its_init(void)
its_cmd_queue_init();
}
+/* must be called after gicv3_enable_defaults */
+void its_enable_defaults(void)
+{
+ int cpu;
+
+ /* Allocate LPI config and pending tables */
+ gicv3_lpi_alloc_tables();
+
+ for_each_present_cpu(cpu)
+ gicv3_lpi_rdist_enable(cpu);
+
+ writel(GITS_CTLR_ENABLE, its_data.base + GITS_CTLR);
+}
--
2.20.1
