The PEBS virtualization enabling in KVM guest will be supported start from
IceLake hardware. This patch introduce a new CPU parameter "pebs" to enable
PEBS feature. The paramter of "pebs" is false by default.
PDCM,DTES64,DTS are needed by PEBS feature. Expose these feature bits to
KVM guest when the KVM support PEBS virtualization and the "pebs" parameter
is true.
Signed-off-by: Luwei Kang <luwei.kang@xxxxxxxxx>
---
hw/i386/pc.c | 1 +
target/i386/cpu.c | 14 ++++++++++++++
target/i386/cpu.h | 7 +++++++
3 files changed, 22 insertions(+)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 96715f8..aeb9fb9 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -316,6 +316,7 @@ GlobalProperty pc_compat_1_5[] = {
{ "Nehalem-" TYPE_X86_CPU, "min-level", "2" },
{ "virtio-net-pci", "any_layout", "off" },
{ TYPE_X86_CPU, "pmu", "on" },
+ { TYPE_X86_CPU, "pebs", "on" },
{ "i440FX-pcihost", "short_root_bus", "0" },
{ "q35-pcihost", "short_root_bus", "0" },
};
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index cc586dc..1ca56de 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -3306,6 +3306,7 @@ static void max_x86_cpu_initfn(Object *obj)
}
object_property_set_bool(OBJECT(cpu), true, "pmu", &error_abort);
+ object_property_set_bool(OBJECT(cpu), true, "pebs", &error_abort);
}
static const TypeInfo max_x86_cpu_type_info = {
@@ -4511,11 +4512,23 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) {
*ecx |= CPUID_EXT_OSXSAVE;
}
+ if (kvm_enabled() && cpu->enable_pmu && cpu->enable_pebs) {
+ *ecx |= kvm_arch_get_supported_cpuid(cs->kvm_state, 0x1, 0, R_ECX) &
+ (CPUID_EXT_PDCM | CPUID_EXT_DTES64);
+ } else {
+ *ecx &= ~(CPUID_EXT_PDCM | CPUID_EXT_DTES64);
+ }
*edx = env->features[FEAT_1_EDX];
if (cs->nr_cores * cs->nr_threads > 1) {
*ebx |= (cs->nr_cores * cs->nr_threads) << 16;
*edx |= CPUID_HT;
}
+ if (kvm_enabled() && cpu->enable_pmu && cpu->enable_pebs) {
+ *edx |= kvm_arch_get_supported_cpuid(cs->kvm_state, 0x1, 0, R_EDX) &
+ CPUID_DTS;
+ } else {
+ *edx &= ~CPUID_DTS;
+ }
break;
case 2:
/* cache info: needed for Pentium Pro compatibility */
@@ -6129,6 +6142,7 @@ static Property x86_cpu_properties[] = {
#endif
DEFINE_PROP_INT32("node-id", X86CPU, node_id, CPU_UNSET_NUMA_NODE_ID),
DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
+ DEFINE_PROP_BOOL("pebs", X86CPU, enable_pebs, false),
DEFINE_PROP_UINT32("hv-spinlocks", X86CPU, hyperv_spinlock_attempts,
HYPERV_SPINLOCK_NEVER_RETRY),
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 5352c9f..398810f 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1664,6 +1664,13 @@ struct X86CPU {
*/
bool enable_pmu;
+ /* Enable PEBS CPUID bits. This can't be enabled by default yet because
+ * it doesn't have ABI stability guarantees, as it passes all PEBS CPUID
+ * bits returned by GET_SUPPORTED_CPUID (that depend on host CPU and kernel
+ * capabilities) directly to the guest.
+ */
+ bool enable_pebs;
+
/* LMCE support can be enabled/disabled via cpu option 'lmce=on/off'. It is
* disabled by default to avoid breaking migration between QEMU with
* different LMCE configurations.
--
1.8.3.1
