On Tue, Feb 25, 2020 at 12:20:03AM +0100, Vitaly Kuznetsov wrote: > Sean Christopherson <sean.j.christopherson@xxxxxxxxx> writes: > > > On Mon, Feb 24, 2020 at 05:32:54PM +0100, Vitaly Kuznetsov wrote: > >> Sean Christopherson <sean.j.christopherson@xxxxxxxxx> writes: > >> > > ... > > > > >> > + > >> > + BUILD_BUG_ON(sizeof(kvm_cpu_caps) > > >> > + sizeof(boot_cpu_data.x86_capability)); > >> > + > >> > + memcpy(&kvm_cpu_caps, &boot_cpu_data.x86_capability, > >> > + sizeof(kvm_cpu_caps)); > >> > + > >> > + kvm_cpu_cap_mask(CPUID_1_EDX, > >> > + F(FPU) | F(VME) | F(DE) | F(PSE) | > >> > + F(TSC) | F(MSR) | F(PAE) | F(MCE) | > >> > + F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) | > >> > + F(MTRR) | F(PGE) | F(MCA) | F(CMOV) | > >> > + F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLUSH) | > >> > + 0 /* Reserved, DS, ACPI */ | F(MMX) | > >> > + F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) | > >> > + 0 /* HTT, TM, Reserved, PBE */ > >> > + ); > >> > + > >> > + kvm_cpu_cap_mask(CPUID_8000_0001_EDX, > >> > + F(FPU) | F(VME) | F(DE) | F(PSE) | > >> > + F(TSC) | F(MSR) | F(PAE) | F(MCE) | > >> > + F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) | > >> > + F(MTRR) | F(PGE) | F(MCA) | F(CMOV) | > >> > + F(PAT) | F(PSE36) | 0 /* Reserved */ | > >> > + f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) | > >> > + F(FXSR) | F(FXSR_OPT) | f_gbpages | F(RDTSCP) | > >> > + 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW) > >> > + ); > >> > + > >> > + kvm_cpu_cap_mask(CPUID_1_ECX, > >> > + /* NOTE: MONITOR (and MWAIT) are emulated as NOP, > >> > + * but *not* advertised to guests via CPUID ! */ > >> > + F(XMM3) | F(PCLMULQDQ) | 0 /* DTES64, MONITOR */ | > >> > + 0 /* DS-CPL, VMX, SMX, EST */ | > >> > + 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ | > >> > + F(FMA) | F(CX16) | 0 /* xTPR Update, PDCM */ | > >> > + F(PCID) | 0 /* Reserved, DCA */ | F(XMM4_1) | > >> > + F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) | > >> > + 0 /* Reserved*/ | F(AES) | F(XSAVE) | 0 /* OSXSAVE */ | F(AVX) | > >> > + F(F16C) | F(RDRAND) > >> > + ); > >> > >> I would suggest we order things by CPUID_NUM here, i.e. > >> > >> CPUID_1_ECX > >> CPUID_1_EDX > >> CPUID_7_1_EAX > >> CPUID_7_0_EBX > >> CPUID_7_ECX > >> CPUID_7_EDX > >> CPUID_D_1_EAX > >> ... > > > > Hmm, generally speaking I agree, but I didn't want to change the ordering > > in this patch when moving the code. Throw a patch on top? Leave as is? > > Something else? > > My line of thought was: it's not a mechanical "s,const u32 > xxx_x86_features =,kvm_cpu_cap_mask...," change, things get moved from > do_cpuid_7_mask() and __do_cpuid_func() so we may as well re-order them, > reviewing-wise it's more or less the same. But honestly, this is very > minor, feel free to leave as-is. Fair enough, I'll throw it into this patch.
