On 2020-02-17 12:52, Mark Rutland wrote:
On Tue, Feb 11, 2020 at 05:48:13PM +0000, Marc Zyngier wrote:
From: Jintack Lim <jintack.lim@xxxxxxxxxx>
Support injecting exceptions and performing exception returns to and
from virtual EL2. This must be done entirely in software except when
taking an exception from vEL0 to vEL2 when the virtual
HCR_EL2.{E2H,TGE}
== {1,1} (a VHE guest hypervisor).
Signed-off-by: Jintack Lim <jintack.lim@xxxxxxxxxx>
Signed-off-by: Christoffer Dall <christoffer.dall@xxxxxxx>
Signed-off-by: Marc Zyngier <maz@xxxxxxxxxx>
---
arch/arm64/include/asm/kvm_arm.h | 17 +++
arch/arm64/include/asm/kvm_emulate.h | 22 ++++
arch/arm64/kvm/Makefile | 2 +
arch/arm64/kvm/emulate-nested.c | 183
+++++++++++++++++++++++++++
arch/arm64/kvm/inject_fault.c | 12 --
arch/arm64/kvm/trace.h | 56 ++++++++
6 files changed, 280 insertions(+), 12 deletions(-)
create mode 100644 arch/arm64/kvm/emulate-nested.c
[...]
+static void enter_el2_exception(struct kvm_vcpu *vcpu, u64 esr_el2,
+ enum exception_type type)
+{
+ trace_kvm_inject_nested_exception(vcpu, esr_el2, type);
+
+ vcpu_write_sys_reg(vcpu, *vcpu_cpsr(vcpu), SPSR_EL2);
+ vcpu_write_sys_reg(vcpu, *vcpu_pc(vcpu), ELR_EL2);
+ vcpu_write_sys_reg(vcpu, esr_el2, ESR_EL2);
+
+ *vcpu_pc(vcpu) = get_el2_except_vector(vcpu, type);
+ /* On an exception, PSTATE.SP becomes 1 */
+ *vcpu_cpsr(vcpu) = PSR_MODE_EL2h;
+ *vcpu_cpsr(vcpu) |= PSR_A_BIT | PSR_F_BIT | PSR_I_BIT | PSR_D_BIT;
+}
This needs to be fixed up to handle the rest of the PSTATE bits.
It should be possible to refactor get_except64_pstate() for that. I
*think* the only differences are bits affects by SCTLR controls, but
someone should audit that -- good thing we added references. :)
Absolutely. It is on my list of things to fix for the next drop. Also,
("arm64: KVM: nv: Honor SCTLR_EL2.SPAN on entering vEL2") should be
folded in there (or simply dropped if we can reuse the EL1 stuff).
Thanks,
M.
--
Jazz is not dead. It just smells funny...
