On 07/02/20 18:37, Sean Christopherson wrote: > Two fixes for 5-level paging bugs with a 100% fatality rate, a patch to > enable 5-level EPT in L1, and additional clean up on top (mostly renames > of functions/variables that caused me no end of confusion when trying to > figure out what was broken). > > Tested fixed kernels at L0, L1 and L2, with most combinations of EPT, > shadow paging, 4-level and 5-level. EPT kvm-unit-tests runs clean in L0. > Patches for kvm-unit-tests incoming to play nice with 5-level nested EPT. > > Ideally patches 1 and 2 would get into 5.6, 5-level paging is quite > broken without them. > > v2: > - Increase the nested EPT array sizes to accomodate 5-level paging in > the patch that adds support for 5-level nested EPT, not in the bug > fix for 5-level shadow paging. > > Sean Christopherson (7): > KVM: nVMX: Use correct root level for nested EPT shadow page tables > KVM: x86/mmu: Fix struct guest_walker arrays for 5-level paging > KVM: nVMX: Allow L1 to use 5-level page walks for nested EPT > KVM: nVMX: Rename nested_ept_get_cr3() to nested_ept_get_eptp() > KVM: nVMX: Rename EPTP validity helper and associated variables > KVM: x86/mmu: Rename kvm_mmu->get_cr3() to ->get_guest_cr3_or_eptp() > KVM: nVMX: Drop unnecessary check on ept caps for execute-only > > arch/x86/include/asm/kvm_host.h | 2 +- > arch/x86/include/asm/vmx.h | 12 +++++++ > arch/x86/kvm/mmu/mmu.c | 35 ++++++++++---------- > arch/x86/kvm/mmu/paging_tmpl.h | 6 ++-- > arch/x86/kvm/svm.c | 10 +++--- > arch/x86/kvm/vmx/nested.c | 58 ++++++++++++++++++++------------- > arch/x86/kvm/vmx/nested.h | 4 +-- > arch/x86/kvm/vmx/vmx.c | 2 ++ > arch/x86/kvm/x86.c | 2 +- > 9 files changed, 79 insertions(+), 52 deletions(-) > Queued 1-2-4-5-7 (for 5.6), thanks! Paolo
