Use the EPT_CAP_* and VPID_CAP_* defines to declare which bits are
reserved in MSR_IA32_VMX_EPT_VPID_CAP. Encoding the reserved bits in
a 64-bit literal is difficult to read, even more difficult to update,
and error prone, as evidenced by the check allowing bit 39 to be '1',
despite it being reserved to zero in Intel's SDM.
No functional change intended.
Signed-off-by: Sean Christopherson <sean.j.christopherson@xxxxxxxxx>
---
x86/vmx.c | 21 ++++++++++++++++++++-
x86/vmx.h | 3 ++-
2 files changed, 22 insertions(+), 2 deletions(-)
diff --git a/x86/vmx.c b/x86/vmx.c
index 0f2521b..3a99d27 100644
--- a/x86/vmx.c
+++ b/x86/vmx.c
@@ -1537,8 +1537,27 @@ static void test_vmx_caps(void)
(val & 0xfffffffffffffc01Ull) == 0,
"MSR_IA32_VMX_VMCS_ENUM");
+ fixed0 = -1ull;
+ fixed0 &= ~(EPT_CAP_WT |
+ EPT_CAP_PWL4 |
+ EPT_CAP_UC |
+ EPT_CAP_WB |
+ EPT_CAP_2M_PAGE |
+ EPT_CAP_1G_PAGE |
+ EPT_CAP_INVEPT |
+ EPT_CAP_AD_FLAG |
+ EPT_CAP_ADV_EPT_INFO |
+ EPT_CAP_INVEPT_SINGLE |
+ EPT_CAP_INVEPT_ALL |
+ VPID_CAP_INVVPID |
+ (1ull << 39) |
+ VPID_CAP_INVVPID_ADDR |
+ VPID_CAP_INVVPID_CXTGLB |
+ VPID_CAP_INVVPID_ALL |
+ VPID_CAP_INVVPID_CXTLOC);
+
val = rdmsr(MSR_IA32_VMX_EPT_VPID_CAP);
- report((val & 0xfffff07ef98cbebeUll) == 0,
+ report((val & fixed0) == 0,
"MSR_IA32_VMX_EPT_VPID_CAP");
}
diff --git a/x86/vmx.h b/x86/vmx.h
index e8035fc..44f0fdd 100644
--- a/x86/vmx.h
+++ b/x86/vmx.h
@@ -587,9 +587,10 @@ enum vm_instruction_error_number {
#define EPT_CAP_2M_PAGE (1ull << 16)
#define EPT_CAP_1G_PAGE (1ull << 17)
#define EPT_CAP_INVEPT (1ull << 20)
+#define EPT_CAP_AD_FLAG (1ull << 21)
+#define EPT_CAP_ADV_EPT_INFO (1ull << 22)
#define EPT_CAP_INVEPT_SINGLE (1ull << 25)
#define EPT_CAP_INVEPT_ALL (1ull << 26)
-#define EPT_CAP_AD_FLAG (1ull << 21)
#define VPID_CAP_INVVPID (1ull << 32)
#define VPID_CAP_INVVPID_ADDR (1ull << 40)
#define VPID_CAP_INVVPID_CXTGLB (1ull << 41)
--
2.24.1
