From: Alexandru Elisei <alexandru.elisei@xxxxxxx>
Writing to the EOIR register before masking the HW mapped timer
interrupt can cause taking another timer interrupt immediately after
exception return. This doesn't happen all the time, because KVM
reevaluates the state of pending HW mapped level sensitive interrupts on
each guest exit. If the second interrupt is pending and a guest exit
occurs after masking the timer interrupt and before the ERET (which
restores PSTATE.I), then KVM removes it.
Move the write after the IMASK bit has been set to prevent this from
happening.
Signed-off-by: Alexandru Elisei <alexandru.elisei@xxxxxxx>
Signed-off-by: Andrew Jones <drjones@xxxxxxxxxx>
---
arm/timer.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/arm/timer.c b/arm/timer.c
index 82f891147b35..b6f9dd10162d 100644
--- a/arm/timer.c
+++ b/arm/timer.c
@@ -157,19 +157,20 @@ static void irq_handler(struct pt_regs *regs)
u32 irqstat = gic_read_iar();
u32 irqnr = gic_iar_irqnr(irqstat);
- if (irqnr != GICC_INT_SPURIOUS)
- gic_write_eoir(irqstat);
-
if (irqnr == PPI(vtimer_info.irq)) {
info = &vtimer_info;
} else if (irqnr == PPI(ptimer_info.irq)) {
info = &ptimer_info;
} else {
+ if (irqnr != GICC_INT_SPURIOUS)
+ gic_write_eoir(irqstat);
report_info("Unexpected interrupt: %d\n", irqnr);
return;
}
info->write_ctl(ARCH_TIMER_CTL_IMASK | ARCH_TIMER_CTL_ENABLE);
+ gic_write_eoir(irqstat);
+
info->irq_received = true;
}
--
2.21.1
