Hi Andre, On 2/3/20 12:20 PM, Andre Przywara wrote: > On Thu, 23 Jan 2020 13:47:53 +0000 > Alexandru Elisei <alexandru.elisei@xxxxxxx> wrote: > >> BAR 0 is an I/O BAR and is registered as an ioport region. Let's set its >> size, so a guest can actually use it. > Well, the whole I/O bar emulates as RAZ/WI, so I would be curious how the guest would actually use it, but specifying the size is surely a good thing, so: Yeah, you're right, I was thinking about ARM where ioport are MMIO and you need to map those address. I'll remove the part about the guest being able to actually use it in the next iteration of the series.. Is it OK if I keep your Reviewed-by? > >> Signed-off-by: Alexandru Elisei <alexandru.elisei@xxxxxxx> > Reviewed-by: Andre Przywara <andre.przywara> > > Cheers, > Andre > >> --- >> hw/vesa.c | 1 + >> 1 file changed, 1 insertion(+) >> >> diff --git a/hw/vesa.c b/hw/vesa.c >> index a665736a76d7..e988c0425946 100644 >> --- a/hw/vesa.c >> +++ b/hw/vesa.c >> @@ -70,6 +70,7 @@ struct framebuffer *vesa__init(struct kvm *kvm) >> >> vesa_base_addr = (u16)r; >> vesa_pci_device.bar[0] = cpu_to_le32(vesa_base_addr | PCI_BASE_ADDRESS_SPACE_IO); >> + vesa_pci_device.bar_size[0] = PCI_IO_SIZE; >> r = device__register(&vesa_device); >> if (r < 0) >> return ERR_PTR(r);
