On Mon, Jan 13, 2020 at 4:05 PM Sean Christopherson <sean.j.christopherson@xxxxxxxxx> wrote: > Another case, which may or may not be possible, is if INIT is recognized > on the same instruction, in which case it takes priority over MTF. SMI > might also be an issue. Don't we already have a priority inversion today when INIT or SMI are coincident with a debug trap on the previous instruction (e.g. single-step trap on an emulated instruction)?
