On Wed, Jan 8, 2020 at 9:20 AM Peter Xu <peterx@xxxxxxxxxx> wrote:
>
> On Thu, Sep 26, 2019 at 04:18:12PM -0700, Ben Gardon wrote:
>
> [...]
>
> > +static int handle_direct_page_fault(struct kvm_vcpu *vcpu,
> > + unsigned long mmu_seq, int write, int map_writable, int level,
> > + gpa_t gpa, gfn_t gfn, kvm_pfn_t pfn, bool prefault)
> > +{
> > + struct direct_walk_iterator iter;
> > + struct kvm_mmu_memory_cache *pf_pt_cache = &vcpu->arch.mmu_page_cache;
> > + u64 *child_pt;
> > + u64 new_pte;
> > + int ret = RET_PF_RETRY;
> > +
> > + direct_walk_iterator_setup_walk(&iter, vcpu->kvm,
> > + kvm_arch_vcpu_memslots_id(vcpu), gpa >> PAGE_SHIFT,
> > + (gpa >> PAGE_SHIFT) + 1, MMU_READ_LOCK);
> > + while (direct_walk_iterator_next_pte(&iter)) {
> > + if (iter.level == level) {
> > + ret = direct_page_fault_handle_target_level(vcpu,
> > + write, map_writable, &iter, pfn,
> > + prefault);
> > +
> > + break;
> > + } else if (!is_present_direct_pte(iter.old_pte) ||
> > + is_large_pte(iter.old_pte)) {
> > + /*
> > + * The leaf PTE for this fault must be mapped at a
> > + * lower level, so a non-leaf PTE must be inserted into
> > + * the paging structure. If the assignment below
> > + * succeeds, it will add the non-leaf PTE and a new
> > + * page of page table memory. Then the iterator can
> > + * traverse into that new page. If the atomic compare/
> > + * exchange fails, the iterator will repeat the current
> > + * PTE, so the only thing this function must do
> > + * differently is return the page table memory to the
> > + * vCPU's fault cache.
> > + */
> > + child_pt = mmu_memory_cache_alloc(pf_pt_cache);
> > + new_pte = generate_nonleaf_pte(child_pt, false);
> > +
> > + if (!direct_walk_iterator_set_pte(&iter, new_pte))
> > + mmu_memory_cache_return(pf_pt_cache, child_pt);
> > + }
> > + }
>
> I have a question on how this will guarantee safe concurrency...
>
> As you mentioned previously somewhere, the design somehow mimics how
> the core mm works with process page tables, and IIUC here the rwlock
> works really like the mmap_sem that we have for the process mm. So
> with the series now we can have multiple page fault happening with
> read lock held of the mmu_lock to reach here.
Ah, I'm sorry if I put that down somewhere. I think that comparing the
MMU rwlock in this series to the core mm mmap_sem was a mistake. I do
not understand the ways in which the core mm uses the mmap_sem enough
to make such a comparison. You're correct that with two faulting vCPUs
we could have page faults on the same address range happening in
parallel. I'll try to elaborate more on why that's safe.
> Then I'm imagining a case where both vcpu threads faulted on the same
> address range while when they wanted to do different things, like: (1)
> vcpu1 thread wanted to map this as a 2M huge page, while (2) vcpu2
> thread wanted to map this as a 4K page.
By vcpu thread, do you mean the page fault / EPT violation handler
wants to map memory at different levels?. As far as I understand,
vCPUs do not have any intent to map a page at a certain level when
they take an EPT violation. The page fault handlers could certainly
want to map the memory at different levels. For example, if guest
memory was backed with 2M hugepages and one vCPU tried to do an
instruction fetch on an unmapped page while another tried to read it,
that should result in the page fault handler for the first vCPU trying
to map at 4K and the other trying to map at 2M, as in your example.
> Then is it possible that
> vcpu2 is faster so it firstly setup the pmd as a page table page (via
> direct_walk_iterator_set_pte above),
This is definitely possible
> then vcpu1 quickly overwrite it
> as a huge page (via direct_page_fault_handle_target_level, level=2),
> then I feel like the previous page table page that setup by vcpu2 can
> be lost unnoticed.
There are two possibilities here. 1.) vCPU2 saw vCPU1's modification
to the PTE during its walk. In this case, vCPU2 should not map the
memory at 2M. (I realize that in this example there is a discrepancy
as there's no NX hugepage support in this RFC. I need to add that in
the next version. In this case, vCPU1 would set a bit in the non-leaf
PTE to indicate it was split to allow X on a constituent 4K entry.)
2.) If vCPU2 did not see vCPU1's modification during its walk, it will
indeed try to map the memory at 2M. However in this case the atomic
cpmxchg on the PTE will fail because vCPU2 did not have the current
value of the PTE. In this case the PTE will be re-read and the walk
will continue or the page fault will be retried. When threads using
the direct walk iterator change PTEs with an atomic cmpxchg, they are
guaranteed to know what the value of the PTE was before the cmpxchg
and so that thread is then responsible for any cleanup associated with
the PTE modification - e.g. freeing pages of page table memory.
> I think general process page table does not have this issue is because
> it has per pmd lock so anyone who changes the pmd or beneath it will
> need to take that. However here we don't have it, instead we only
> depend on the atomic ops, which seems to be not enough for this?
I think that atomic ops (plus rcu to ensure no use-after-free) are
enough in this case, but I could definitely be wrong. If your concern
about the race requires the NX hugepages stuff, I need to get on top
of sending out those patches. If you can think of a race that doesn't
require that, I'd be very excited to hear it.
> Thanks,
>
> > + direct_walk_iterator_end_traversal(&iter);
> > +
> > + /* If emulating, flush this vcpu's TLB. */
> > + if (ret == RET_PF_EMULATE)
> > + kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
> > +
> > + return ret;
> > +}
>
> --
> Peter Xu
>
