On Tue, Jan 07, 2020 at 05:51:51PM -0600, Tom Lendacky wrote: > On 1/7/20 5:31 PM, Sean Christopherson wrote: > > AIUI, using phys_bits=48, then the standard scenario is Cbit=47 and some > > additional bits 46:M are reserved. Applying that logic to phys_bits=52, > > then Cbit=51 and bits 50:M are reserved, so there's a collision but it's > > There's no requirement that the C-bit correspond to phys_bits. So, for > example, you can have C-bit=51 and phys_bits=48 and so 47:M are reserved. But then using blindly using x86_phys_bits would break if the PA bits aren't reduced, e.g. C-bit=47 and phys_bits=47. AFAICT, there's no requirement that there be reduced PA bits when there is a C-bit. I'm guessing there aren't plans to ship such CPUs, but I don't see anything in the APM to prevent such a scenario. Maybe the least painful approach would be to go with a version of this patch and add a check that there are indeeded reserved/reduced bits? Probably with a WARN_ON_ONCE if the check fails.
