From: Alexandru Elisei <alexandru.elisei@xxxxxxx> There's really no need to invalidate the TLB entries for all CPUs when enabling the MMU for the current CPU, so use the non-shareable version of the TLBI operation (and downgrade the DSB accordingly). Signed-off-by: Alexandru Elisei <alexandru.elisei@xxxxxxx> Signed-off-by: Andrew Jones <drjones@xxxxxxxxxx> --- arm/cstart64.S | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arm/cstart64.S b/arm/cstart64.S index b0e8baa1a23a..6f49506ca19b 100644 --- a/arm/cstart64.S +++ b/arm/cstart64.S @@ -160,8 +160,8 @@ halt: .globl asm_mmu_enable asm_mmu_enable: ic iallu // I+BTB cache invalidate - tlbi vmalle1is // invalidate I + D TLBs - dsb ish + tlbi vmalle1 // invalidate I + D TLBs + dsb nsh /* TCR */ ldr x1, =TCR_TxSZ(VA_BITS) | \ -- 2.21.0
