> From: Lu Baolu < baolu.lu@xxxxxxxxxxxxxxx > > Sent: Tuesday, December 17, 2019 10:04 AM > To: Liu, Yi L <yi.l.liu@xxxxxxxxx>; Joerg Roedel <joro@xxxxxxxxxx>; David > Woodhouse <dwmw2@xxxxxxxxxxxxx>; Alex Williamson > <alex.williamson@xxxxxxxxxx> > Subject: Re: [PATCH v3 4/6] iommu/vt-d: Setup pasid entries for iova over first level > > Hi Yi, > > On 12/15/19 5:37 PM, Liu, Yi L wrote: > >> XD (bit 63) is only for the first level, and SNP (bit 11) is only for > >> second level, right? I think we need to always set XD bit for IOVA over FL case. > thoughts? > > Oops, I made a mistake here. Please forget SNP bit, there is no way to > > control SNP with first level page table.:-) > > > > Actually, it is execute (bit 1) of second level page table which I wanted to say. > > If software sets R/W/X permission to an IOVA, with IOVA over second > > level page table, it will set bit 1. However, if IOVA is over first > > level page table, it may need to clear XD bit. This is what I want to > > say here. If IOVA doesn’t allow execute permission, it's ok to always > > set XD bit for IOVA over FL case. But I would like to do it just as > > what we did for R/W permission. R/W permission relies on the permission > configured by the page map caller. right? > > Got your point. > > Current driver always cleard X (bit 2) in the second level page table. > So we will always set XD bit (bit 63) in the first level page table. yes, I also noticed X (bit 2) is not used in intel-iommu driver. So I know why you set XD for IOVA over FL case. But it's a little bit weird to hard code it. That's why I suggested to relay page map caller's permission input. > If we decide to use the X permission, we need a separated patch, right? sure, it would be a separate patch since current code doesn’t apply X permission. Regards, Yi Liu
