We've tested this on Skylake, Broadwell, Haswell, Ivybridge, Sandybridge, and probably some newer platforms. I haven't gone digging for any super old hardware to test on. On Mon, Dec 2, 2019 at 3:46 PM Sean Christopherson <sean.j.christopherson@xxxxxxxxx> wrote: > > On Thu, Sep 26, 2019 at 04:18:06PM -0700, Ben Gardon wrote: > > If page table memory is freed before a TLB flush, it can result in > > improper guest access to memory through paging structure caches. > > Specifically, until a TLB flush, memory that was part of the paging > > structure could be used by the hardware for address translation if a > > partial walk leading to it is stored in the paging structure cache. Ensure > > that there is a TLB flush before page table memory is freed by > > transferring disconnected pages to a disconnected list, and on a flush > > transferring a snapshot of the disconnected list to a free list. The free > > list is processed asynchronously to avoid slowing TLB flushes. > > Tangentially realted to TLB flushing, what generations of CPUs have you > tested this on? I don't have any specific concerns, but ideally it'd be > nice to get testing cycles on older hardware before merging. Thankfully > TDP-only eliminates ridiculously old hardware :-)
