On 28/11/2019 18:04, Alexandru Elisei wrote:
Hi,
> flush_tlb_all performs a TLBIALL, which affects only the executing PE; fix
> that by executing a TLBIALLIS. Note that virtualization extensions imply
> the multiprocessing extensions, so we're safe to use that instruction.
>
> While we're at it, let's add a comment to flush_dcache_addr stating what
> instruction is uses (unsurprisingly, it's a dcache clean and invalidate to
> PoC).
Good idea, but for people not fluent in ARMish I might be even better to
actually spell that out there in the comment, also mentioning VA, maybe.
Apart from that this looks good, also checked the encodings.
Cheers,
Andre
>
> Signed-off-by: Alexandru Elisei <alexandru.elisei@xxxxxxx>
> ---
> lib/arm/asm/mmu.h | 7 +++++--
> 1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/lib/arm/asm/mmu.h b/lib/arm/asm/mmu.h
> index 361f3cdcc3d5..7c9ee3dbc079 100644
> --- a/lib/arm/asm/mmu.h
> +++ b/lib/arm/asm/mmu.h
> @@ -25,8 +25,10 @@ static inline void local_flush_tlb_all(void)
>
> static inline void flush_tlb_all(void)
> {
> - //TODO
> - local_flush_tlb_all();
> + /* TLBIALLIS */
> + asm volatile("mcr p15, 0, %0, c8, c3, 0" :: "r" (0));
> + dsb();
> + isb();
> }
>
> static inline void flush_tlb_page(unsigned long vaddr)
> @@ -39,6 +41,7 @@ static inline void flush_tlb_page(unsigned long vaddr)
>
> static inline void flush_dcache_addr(unsigned long vaddr)
> {
> + /* DCCIMVAC */
> asm volatile("mcr p15, 0, %0, c7, c14, 1" :: "r" (vaddr));
> }
>
>
